Search

Blair M. Johnson

Examiner (ID: 4242, Phone: (571)272-6830 , Office: P/3634 )

Most Active Art Unit
3634
Art Unit(s)
3634, 3505, 3623, 3509
Total Applications
3198
Issued Applications
2330
Pending Applications
84
Abandoned Applications
790

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19704732 [patent_doc_number] => 12198778 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-14 [patent_title] => Memory controllers and memory systems including the same [patent_app_type] => utility [patent_app_number] => 18/351709 [patent_app_country] => US [patent_app_date] => 2023-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 22 [patent_no_of_words] => 13424 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18351709 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/351709
Memory controllers and memory systems including the same Jul 12, 2023 Issued
Array ( [id] => 19595650 [patent_doc_number] => 12153492 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-11-26 [patent_title] => Managing error corrections for memory systems [patent_app_type] => utility [patent_app_number] => 18/350877 [patent_app_country] => US [patent_app_date] => 2023-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 12981 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18350877 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/350877
Managing error corrections for memory systems Jul 11, 2023 Issued
Array ( [id] => 18772847 [patent_doc_number] => 20230367673 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-16 [patent_title] => SYSTEM AND METHOD OF REDUCING LOGIC FOR MULTI-BIT ERROR CORRECTING CODES [patent_app_type] => utility [patent_app_number] => 18/350776 [patent_app_country] => US [patent_app_date] => 2023-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6617 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18350776 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/350776
System and method of reducing logic for multi-bit error correcting codes Jul 11, 2023 Issued
Array ( [id] => 19705587 [patent_doc_number] => 12199637 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-14 [patent_title] => Accelerated erasure coding system and method [patent_app_type] => utility [patent_app_number] => 18/213766 [patent_app_country] => US [patent_app_date] => 2023-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 16366 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18213766 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/213766
Accelerated erasure coding system and method Jun 22, 2023 Issued
Array ( [id] => 19661811 [patent_doc_number] => 20240428876 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-26 [patent_title] => SYSTEMS AND METHODS FOR TESTING ERROR CORRECTION CODE (ECC) LOGIC OF AUTOMOTIVE SAFETY SYSTEMS FOR FAULTS [patent_app_type] => utility [patent_app_number] => 18/338635 [patent_app_country] => US [patent_app_date] => 2023-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10722 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18338635 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/338635
Systems and methods for testing error correction code (ECC) logic of automotive safety systems for faults Jun 20, 2023 Issued
Array ( [id] => 19639915 [patent_doc_number] => 12170533 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-17 [patent_title] => Semiconductor memory device and method of operating semiconductor memory device [patent_app_type] => utility [patent_app_number] => 18/336285 [patent_app_country] => US [patent_app_date] => 2023-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 27 [patent_no_of_words] => 13463 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18336285 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/336285
Semiconductor memory device and method of operating semiconductor memory device Jun 15, 2023 Issued
Array ( [id] => 20145650 [patent_doc_number] => 12379992 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-05 [patent_title] => System and method for protecting data [patent_app_type] => utility [patent_app_number] => 18/334938 [patent_app_country] => US [patent_app_date] => 2023-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2930 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18334938 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/334938
System and method for protecting data Jun 13, 2023 Issued
Array ( [id] => 19506072 [patent_doc_number] => 12117488 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-10-15 [patent_title] => Multiple clock and clock cycle selection for x-tolerant logic built in self test (XLBIST) [patent_app_type] => utility [patent_app_number] => 18/208886 [patent_app_country] => US [patent_app_date] => 2023-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8175 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18208886 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/208886
Multiple clock and clock cycle selection for x-tolerant logic built in self test (XLBIST) Jun 12, 2023 Issued
Array ( [id] => 19926044 [patent_doc_number] => 12300336 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-13 [patent_title] => Media scan in memory systems [patent_app_type] => utility [patent_app_number] => 18/327642 [patent_app_country] => US [patent_app_date] => 2023-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3866 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18327642 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/327642
Media scan in memory systems May 31, 2023 Issued
Array ( [id] => 20145652 [patent_doc_number] => 12379994 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-05 [patent_title] => Memory address translation for data protection and recovery [patent_app_type] => utility [patent_app_number] => 18/204821 [patent_app_country] => US [patent_app_date] => 2023-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3539 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18204821 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/204821
Memory address translation for data protection and recovery May 31, 2023 Issued
Array ( [id] => 19679102 [patent_doc_number] => 12190973 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-07 [patent_title] => Memory device performing sensing operation and method of operating the same [patent_app_type] => utility [patent_app_number] => 18/325999 [patent_app_country] => US [patent_app_date] => 2023-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7265 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18325999 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/325999
Memory device performing sensing operation and method of operating the same May 30, 2023 Issued
Array ( [id] => 19616566 [patent_doc_number] => 20240402246 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-05 [patent_title] => ERROR PROTECTION ANALYSIS OF AN INTEGRATED CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/326717 [patent_app_country] => US [patent_app_date] => 2023-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6588 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18326717 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/326717
Error protection analysis of an integrated circuit May 30, 2023 Issued
Array ( [id] => 19466442 [patent_doc_number] => 20240320112 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => METHOD AND APPARATUS TO INJECT ERRORS IN A MEMORY BLOCK AND VALIDATE DIAGNOSTIC ACTIONS FOR MEMORY BUILT-IN-SELF-TEST (MBIST) FAILURES [patent_app_type] => utility [patent_app_number] => 18/318840 [patent_app_country] => US [patent_app_date] => 2023-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8056 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18318840 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/318840
Method and apparatus to inject errors in a memory block and validate diagnostic actions for memory built-in-self-test (MBIST) failures May 16, 2023 Issued
Array ( [id] => 19334393 [patent_doc_number] => 20240248823 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-25 [patent_title] => CONTROLLER, STORAGE DEVICE AND TEST SYSTEM [patent_app_type] => utility [patent_app_number] => 18/318655 [patent_app_country] => US [patent_app_date] => 2023-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7826 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18318655 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/318655
Controller, storage device and test system May 15, 2023 Issued
Array ( [id] => 19964655 [patent_doc_number] => 12334170 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-17 [patent_title] => Operating and testing semiconductor devices [patent_app_type] => utility [patent_app_number] => 18/314508 [patent_app_country] => US [patent_app_date] => 2023-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 4800 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18314508 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/314508
Operating and testing semiconductor devices May 8, 2023 Issued
Array ( [id] => 18881385 [patent_doc_number] => 20240004754 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-04 [patent_title] => SEMICONDUCTOR DEVICE WITH USER DEFINED OPERATIONS AND ASSOCIATED METHODS AND SYSTEMS [patent_app_type] => utility [patent_app_number] => 18/313656 [patent_app_country] => US [patent_app_date] => 2023-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10827 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18313656 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/313656
Semiconductor device with user defined operations and associated methods and systems May 7, 2023 Issued
Array ( [id] => 18600894 [patent_doc_number] => 20230275697 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-31 [patent_title] => POLAR CODING SYSTEMS, PROCEDURES, AND SIGNALING [patent_app_type] => utility [patent_app_number] => 18/143394 [patent_app_country] => US [patent_app_date] => 2023-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19861 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18143394 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/143394
Polar coding systems, procedures, and signaling May 3, 2023 Issued
Array ( [id] => 19679106 [patent_doc_number] => 12190977 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-07 [patent_title] => Memory test system and memory test method [patent_app_type] => utility [patent_app_number] => 18/127775 [patent_app_country] => US [patent_app_date] => 2023-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4799 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18127775 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/127775
Memory test system and memory test method Mar 28, 2023 Issued
Array ( [id] => 20130961 [patent_doc_number] => 12373274 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-29 [patent_title] => Selective re-execution of instruction streams for reliability [patent_app_type] => utility [patent_app_number] => 18/123567 [patent_app_country] => US [patent_app_date] => 2023-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 1112 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18123567 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/123567
Selective re-execution of instruction streams for reliability Mar 19, 2023 Issued
Array ( [id] => 19465605 [patent_doc_number] => 20240319275 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => CONTROLLING STORAGE OF TEST DATA BASED ON PRIOR TEST PROGRAM EXECUTION [patent_app_type] => utility [patent_app_number] => 18/123680 [patent_app_country] => US [patent_app_date] => 2023-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6445 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -28 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18123680 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/123680
Controlling storage of test data based on prior test program execution Mar 19, 2023 Issued
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