Search

Bo Bin Jang

Examiner (ID: 12239, Phone: (571)270-0271 , Office: P/2894 )

Most Active Art Unit
2894
Art Unit(s)
2894, 2818
Total Applications
768
Issued Applications
624
Pending Applications
85
Abandoned Applications
74

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 13229033 [patent_doc_number] => 10128299 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-11-13 [patent_title] => Manufacturing method of image sensor including source follower contact to floating diffusion [patent_app_type] => utility [patent_app_number] => 15/728893 [patent_app_country] => US [patent_app_date] => 2017-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3183 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15728893 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/728893
Manufacturing method of image sensor including source follower contact to floating diffusion Oct 9, 2017 Issued
Array ( [id] => 12631512 [patent_doc_number] => 20180102334 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-12 [patent_title] => WAFER LAMINATE AND METHOD OF PRODUCING THE SAME [patent_app_type] => utility [patent_app_number] => 15/728958 [patent_app_country] => US [patent_app_date] => 2017-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10812 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15728958 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/728958
Wafer laminate and method of producing the same Oct 9, 2017 Issued
Array ( [id] => 15922131 [patent_doc_number] => 10658314 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-19 [patent_title] => Wafer laminate, method for production thereof, and adhesive composition for wafer laminate [patent_app_type] => utility [patent_app_number] => 15/728846 [patent_app_country] => US [patent_app_date] => 2017-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 9313 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15728846 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/728846
Wafer laminate, method for production thereof, and adhesive composition for wafer laminate Oct 9, 2017 Issued
Array ( [id] => 17063231 [patent_doc_number] => 11107843 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-31 [patent_title] => Array substrate, manufacturing method thereof, and display panel [patent_app_type] => utility [patent_app_number] => 15/775086 [patent_app_country] => US [patent_app_date] => 2017-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 8866 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15775086 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/775086
Array substrate, manufacturing method thereof, and display panel Oct 8, 2017 Issued
Array ( [id] => 14738235 [patent_doc_number] => 10388527 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-20 [patent_title] => Method of manufacturing semiconductor device [patent_app_type] => utility [patent_app_number] => 15/726603 [patent_app_country] => US [patent_app_date] => 2017-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4341 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 268 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15726603 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/726603
Method of manufacturing semiconductor device Oct 5, 2017 Issued
Array ( [id] => 14163813 [patent_doc_number] => 20190109009 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-11 [patent_title] => METHOD FOR SELECTIVELY DEPOSITING A METALLIC FILM ON A SUBSTRATE [patent_app_type] => utility [patent_app_number] => 15/726222 [patent_app_country] => US [patent_app_date] => 2017-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9086 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15726222 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/726222
Method for selectively depositing a metallic film on a substrate Oct 4, 2017 Issued
Array ( [id] => 15250421 [patent_doc_number] => 10510739 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-17 [patent_title] => Method of providing layout design of SRAM cell [patent_app_type] => utility [patent_app_number] => 15/726334 [patent_app_country] => US [patent_app_date] => 2017-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 9868 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15726334 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/726334
Method of providing layout design of SRAM cell Oct 4, 2017 Issued
Array ( [id] => 16660717 [patent_doc_number] => 20210057354 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-25 [patent_title] => WARPAGE MITIGATION STRUCTURES CREATED ON SUBSTRATE USING HIGH THROUGHPUT ADDITIVE MANUFACTURING [patent_app_type] => utility [patent_app_number] => 16/638741 [patent_app_country] => US [patent_app_date] => 2017-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19691 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16638741 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/638741
Warpage mitigation structures created on substrate using high throughput additive manufacturing Sep 29, 2017 Issued
Array ( [id] => 17105839 [patent_doc_number] => 11126048 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-21 [patent_title] => Array substrate and display device [patent_app_type] => utility [patent_app_number] => 15/776455 [patent_app_country] => US [patent_app_date] => 2017-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4568 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15776455 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/776455
Array substrate and display device Sep 21, 2017 Issued
Array ( [id] => 14762673 [patent_doc_number] => 10392725 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-27 [patent_title] => Method for depositing silicon feedstock material, silicon wafer, solar cell and PV module [patent_app_type] => utility [patent_app_number] => 15/708227 [patent_app_country] => US [patent_app_date] => 2017-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 7127 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15708227 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/708227
Method for depositing silicon feedstock material, silicon wafer, solar cell and PV module Sep 18, 2017 Issued
Array ( [id] => 13936095 [patent_doc_number] => 20190051563 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-14 [patent_title] => METHODS, APPARATUS, AND MANUFACTURING SYSTEM FOR SELF-ALIGNED PATTERNING OF A VERTICAL TRANSISTOR [patent_app_type] => utility [patent_app_number] => 15/676005 [patent_app_country] => US [patent_app_date] => 2017-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7507 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15676005 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/676005
Methods, apparatus, and manufacturing system for self-aligned patterning of a vertical transistor Aug 13, 2017 Issued
Array ( [id] => 17284133 [patent_doc_number] => 11201176 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-12-14 [patent_title] => Array substrate, display apparatus, and method of fabricating array substrate [patent_app_type] => utility [patent_app_number] => 16/070098 [patent_app_country] => US [patent_app_date] => 2017-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 5624 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16070098 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/070098
Array substrate, display apparatus, and method of fabricating array substrate Aug 7, 2017 Issued
Array ( [id] => 16218724 [patent_doc_number] => 10734547 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-04 [patent_title] => Semiconductor device and semiconductor device package comprising same [patent_app_type] => utility [patent_app_number] => 16/312937 [patent_app_country] => US [patent_app_date] => 2017-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 26 [patent_no_of_words] => 16712 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16312937 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/312937
Semiconductor device and semiconductor device package comprising same Jun 22, 2017 Issued
Array ( [id] => 16645660 [patent_doc_number] => 10923528 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-16 [patent_title] => Optoelectronic device comprising pixels with improved contrast and brightness [patent_app_type] => utility [patent_app_number] => 16/313005 [patent_app_country] => US [patent_app_date] => 2017-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 41 [patent_no_of_words] => 11857 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 261 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16313005 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/313005
Optoelectronic device comprising pixels with improved contrast and brightness Jun 21, 2017 Issued
Array ( [id] => 15024283 [patent_doc_number] => 20190323146 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-24 [patent_title] => GROUP III NITRIDE LAMINATE AND VERTICAL SEMICONDUCTOR DEVICE HAVING THE LAMINATE [patent_app_type] => utility [patent_app_number] => 16/312885 [patent_app_country] => US [patent_app_date] => 2017-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6165 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 28 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16312885 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/312885
Group III nitride laminate and vertical semiconductor device having the laminate Jun 18, 2017 Issued
Array ( [id] => 11959315 [patent_doc_number] => 20170263467 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-14 [patent_title] => 'METHODS OF FORMING A PORTION OF A MEMORY ARRAY HAVING A CONDUCTOR HAVING A VARIABLE CONCENTRATION OF GERMANIUM' [patent_app_type] => utility [patent_app_number] => 15/606080 [patent_app_country] => US [patent_app_date] => 2017-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 10488 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15606080 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/606080
Methods of forming a portion of a memory array having a conductor having a variable concentration of germanium May 25, 2017 Issued
Array ( [id] => 16132633 [patent_doc_number] => 10700084 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-30 [patent_title] => Vertical memory devices [patent_app_type] => utility [patent_app_number] => 15/601501 [patent_app_country] => US [patent_app_date] => 2017-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 48 [patent_figures_cnt] => 48 [patent_no_of_words] => 9060 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15601501 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/601501
Vertical memory devices May 21, 2017 Issued
Array ( [id] => 15468253 [patent_doc_number] => 10549988 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-04 [patent_title] => Wafer-level package with enhanced performance [patent_app_type] => utility [patent_app_number] => 15/601858 [patent_app_country] => US [patent_app_date] => 2017-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 5941 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15601858 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/601858
Wafer-level package with enhanced performance May 21, 2017 Issued
Array ( [id] => 15468253 [patent_doc_number] => 10549988 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-04 [patent_title] => Wafer-level package with enhanced performance [patent_app_type] => utility [patent_app_number] => 15/601858 [patent_app_country] => US [patent_app_date] => 2017-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 5941 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15601858 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/601858
Wafer-level package with enhanced performance May 21, 2017 Issued
Array ( [id] => 15468253 [patent_doc_number] => 10549988 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-04 [patent_title] => Wafer-level package with enhanced performance [patent_app_type] => utility [patent_app_number] => 15/601858 [patent_app_country] => US [patent_app_date] => 2017-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 5941 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15601858 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/601858
Wafer-level package with enhanced performance May 21, 2017 Issued
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