Search

Bong-sook Baek

Examiner (ID: 5880, Phone: (571)270-5863 , Office: P/1621 )

Most Active Art Unit
1611
Art Unit(s)
1621, 1629, 1611, 4161, 1614
Total Applications
1174
Issued Applications
495
Pending Applications
84
Abandoned Applications
612

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19348893 [patent_doc_number] => 20240257857 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-01 [patent_title] => APPARATUS AND METHOD FOR PERFORMING TARGET REFRESH OPERATION [patent_app_type] => utility [patent_app_number] => 18/635208 [patent_app_country] => US [patent_app_date] => 2024-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10379 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18635208 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/635208
Apparatus and method for performing target refresh operation Apr 14, 2024 Issued
Array ( [id] => 20080559 [patent_doc_number] => 12354634 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-08 [patent_title] => Transistorless memory cell [patent_app_type] => utility [patent_app_number] => 18/632358 [patent_app_country] => US [patent_app_date] => 2024-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 20 [patent_no_of_words] => 4231 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18632358 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/632358
Transistorless memory cell Apr 10, 2024 Issued
Array ( [id] => 19515410 [patent_doc_number] => 20240347096 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-17 [patent_title] => Usage-Based Disturbance Counter Clearance [patent_app_type] => utility [patent_app_number] => 18/628127 [patent_app_country] => US [patent_app_date] => 2024-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13278 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18628127 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/628127
Usage-Based Disturbance Counter Clearance Apr 4, 2024 Pending
Array ( [id] => 19748014 [patent_doc_number] => 20250036579 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-30 [patent_title] => MEMORY DEVICE WITH MULTIPLE PHYSICAL INTERFACES [patent_app_type] => utility [patent_app_number] => 18/625212 [patent_app_country] => US [patent_app_date] => 2024-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6282 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18625212 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/625212
MEMORY DEVICE WITH MULTIPLE PHYSICAL INTERFACES Apr 2, 2024 Pending
Array ( [id] => 20235506 [patent_doc_number] => 20250292825 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-18 [patent_title] => DYNAMIC RANDOM-ACCESS MEMORY (DRAM) DEVICE [patent_app_type] => utility [patent_app_number] => 18/603154 [patent_app_country] => US [patent_app_date] => 2024-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18603154 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/603154
Dynamic random-access memory (DRAM) device Mar 11, 2024 Issued
Array ( [id] => 19406862 [patent_doc_number] => 20240290373 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-29 [patent_title] => GENERATING ACCESS LINE VOLTAGES [patent_app_type] => utility [patent_app_number] => 18/598888 [patent_app_country] => US [patent_app_date] => 2024-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13341 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18598888 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/598888
GENERATING ACCESS LINE VOLTAGES Mar 6, 2024 Pending
Array ( [id] => 19237037 [patent_doc_number] => 20240194232 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-13 [patent_title] => SEMICONDUCTOR DEVICE INCLUDING INTERNAL TRANSMISSION PATH AND STACKED SEMICONDUCTOR DEVICE USING THE SAME [patent_app_type] => utility [patent_app_number] => 18/587961 [patent_app_country] => US [patent_app_date] => 2024-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13975 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18587961 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/587961
Semiconductor device including internal transmission path and stacked semiconductor device using the same Feb 26, 2024 Issued
Array ( [id] => 19392489 [patent_doc_number] => 20240282359 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-22 [patent_title] => SEMICONDUCTOR STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 18/582433 [patent_app_country] => US [patent_app_date] => 2024-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7267 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18582433 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/582433
SEMICONDUCTOR STORAGE DEVICE Feb 19, 2024 Pending
Array ( [id] => 19392498 [patent_doc_number] => 20240282368 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-22 [patent_title] => BINARY NEURAL NETWORK HARDWARE APPARATUS [patent_app_type] => utility [patent_app_number] => 18/443221 [patent_app_country] => US [patent_app_date] => 2024-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4516 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18443221 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/443221
BINARY NEURAL NETWORK HARDWARE APPARATUS Feb 14, 2024 Pending
Array ( [id] => 20167626 [patent_doc_number] => 20250259673 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-14 [patent_title] => CIRCUITRY TO DETECT CYCLE COUNT FOR INCREASED THROUGHPUT READS AND WRITE OPERATIONS FOR MEMORY [patent_app_type] => utility [patent_app_number] => 18/436330 [patent_app_country] => US [patent_app_date] => 2024-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2275 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18436330 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/436330
CIRCUITRY TO DETECT CYCLE COUNT FOR INCREASED THROUGHPUT READS AND WRITE OPERATIONS FOR MEMORY Feb 7, 2024 Pending
Array ( [id] => 20153167 [patent_doc_number] => 20250253005 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-07 [patent_title] => MEMORY DEVICE AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/435941 [patent_app_country] => US [patent_app_date] => 2024-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1149 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18435941 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/435941
MEMORY DEVICE AND OPERATING METHOD THEREOF Feb 6, 2024 Pending
Array ( [id] => 20153157 [patent_doc_number] => 20250252995 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-07 [patent_title] => MEMORY DEVICE AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/435785 [patent_app_country] => US [patent_app_date] => 2024-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2662 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18435785 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/435785
MEMORY DEVICE AND OPERATING METHOD THEREOF Feb 6, 2024 Pending
Array ( [id] => 20124248 [patent_doc_number] => 20250239279 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-24 [patent_title] => MEMORY DEVICE AND METHOD OF CONTROLLING EQUIVALENT RESISTANCE OF BIT LINE OR SOURCE LINE CORRESPONDING TO WORD LINE OF THE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/430585 [patent_app_country] => US [patent_app_date] => 2024-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18430585 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/430585
MEMORY DEVICE AND METHOD OF CONTROLLING EQUIVALENT RESISTANCE OF BIT LINE OR SOURCE LINE CORRESPONDING TO WORD LINE OF THE MEMORY DEVICE Jan 31, 2024 Pending
Array ( [id] => 20530164 [patent_doc_number] => 12548605 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-10 [patent_title] => Interface circuit and semiconductor device including the same [patent_app_type] => utility [patent_app_number] => 18/408571 [patent_app_country] => US [patent_app_date] => 2024-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 1 [patent_no_of_words] => 925 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18408571 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/408571
Interface circuit and semiconductor device including the same Jan 9, 2024 Issued
Array ( [id] => 20507908 [patent_doc_number] => 12542190 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-03 [patent_title] => Selectable trim settings on a memory device [patent_app_type] => utility [patent_app_number] => 18/393284 [patent_app_country] => US [patent_app_date] => 2023-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 0 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18393284 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/393284
Selectable trim settings on a memory device Dec 20, 2023 Issued
Array ( [id] => 19269022 [patent_doc_number] => 20240212726 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-27 [patent_title] => DEVICE INCLUDING INPUT/OUTPUT CIRCUIT, A SYSTEM INCLUDING THE DEVICE, AND AN OPERATING METHOD OF THE SYSTEM [patent_app_type] => utility [patent_app_number] => 18/544550 [patent_app_country] => US [patent_app_date] => 2023-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8567 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18544550 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/544550
DEVICE INCLUDING INPUT/OUTPUT CIRCUIT, A SYSTEM INCLUDING THE DEVICE, AND AN OPERATING METHOD OF THE SYSTEM Dec 18, 2023 Pending
Array ( [id] => 19100778 [patent_doc_number] => 20240120006 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-11 [patent_title] => THREE-STATE PROGRAMMING OF MEMORY CELLS [patent_app_type] => utility [patent_app_number] => 18/545245 [patent_app_country] => US [patent_app_date] => 2023-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7787 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18545245 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/545245
Three-state programming of memory cells Dec 18, 2023 Issued
Array ( [id] => 19546121 [patent_doc_number] => 20240363157 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-31 [patent_title] => MEMORY DEVICE FOR BIASING DUMMY GLOBAL BITLINE [patent_app_type] => utility [patent_app_number] => 18/538260 [patent_app_country] => US [patent_app_date] => 2023-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4794 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18538260 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/538260
MEMORY DEVICE FOR BIASING DUMMY GLOBAL BITLINE Dec 12, 2023 Pending
Array ( [id] => 19237054 [patent_doc_number] => 20240194249 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-13 [patent_title] => METHOD FOR CONTROLLING NAND FLASH MEMORY TO COMPLETE NEURAL NETWORK OPERATION [patent_app_type] => utility [patent_app_number] => 18/534957 [patent_app_country] => US [patent_app_date] => 2023-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6496 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18534957 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/534957
Method for controlling NAND flash memory to complete neural network operation Dec 10, 2023 Issued
Array ( [id] => 20530165 [patent_doc_number] => 12548606 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-10 [patent_title] => Multi-mode compatible ZQ calibration circuit in memory device [patent_app_type] => utility [patent_app_number] => 18/528339 [patent_app_country] => US [patent_app_date] => 2023-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 2430 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18528339 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/528339
Multi-mode compatible ZQ calibration circuit in memory device Dec 3, 2023 Issued
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