Search

Bong-sook Baek

Examiner (ID: 5880, Phone: (571)270-5863 , Office: P/1621 )

Most Active Art Unit
1611
Art Unit(s)
1621, 1629, 1611, 4161, 1614
Total Applications
1174
Issued Applications
495
Pending Applications
84
Abandoned Applications
612

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17737727 [patent_doc_number] => 20220223189 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-14 [patent_title] => LARGE FILE INTEGRITY TECHNIQUES [patent_app_type] => utility [patent_app_number] => 17/708629 [patent_app_country] => US [patent_app_date] => 2022-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9040 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17708629 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/708629
Large file integrity techniques Mar 29, 2022 Issued
Array ( [id] => 18661024 [patent_doc_number] => 20230307037 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-28 [patent_title] => CLUSTERING FOR READ THRESHOLDS HISTORY TABLE COMPRESSION IN NAND STORAGE SYSTEMS [patent_app_type] => utility [patent_app_number] => 17/703199 [patent_app_country] => US [patent_app_date] => 2022-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12470 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17703199 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/703199
Clustering for read thresholds history table compression in NAND storage systems Mar 23, 2022 Issued
Array ( [id] => 19796036 [patent_doc_number] => 12237001 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-25 [patent_title] => Apparatuses including output drivers and methods for providing output data signals [patent_app_type] => utility [patent_app_number] => 17/700289 [patent_app_country] => US [patent_app_date] => 2022-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6818 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17700289 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/700289
Apparatuses including output drivers and methods for providing output data signals Mar 20, 2022 Issued
Array ( [id] => 18998925 [patent_doc_number] => 11915779 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-27 [patent_title] => Sense amplifier schemes for accessing memory cells [patent_app_type] => utility [patent_app_number] => 17/685196 [patent_app_country] => US [patent_app_date] => 2022-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 31629 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17685196 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/685196
Sense amplifier schemes for accessing memory cells Mar 1, 2022 Issued
Array ( [id] => 20243943 [patent_doc_number] => 12424273 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-23 [patent_title] => Storage circuit provided with variable resistance type elements [patent_app_type] => utility [patent_app_number] => 17/653033 [patent_app_country] => US [patent_app_date] => 2022-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 39 [patent_no_of_words] => 7889 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 347 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17653033 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/653033
Storage circuit provided with variable resistance type elements Feb 28, 2022 Issued
Array ( [id] => 17779840 [patent_doc_number] => 20220246190 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-04 [patent_title] => GIANT SPIN HALL-BASED COMPACT NEUROMORPHIC CELL OPTIMIZED FOR DIFFERENTIAL READ INFERENCE [patent_app_type] => utility [patent_app_number] => 17/679601 [patent_app_country] => US [patent_app_date] => 2022-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6274 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17679601 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/679601
Giant spin hall-based compact neuromorphic cell optimized for differential read inference Feb 23, 2022 Issued
Array ( [id] => 18555009 [patent_doc_number] => 20230253025 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-10 [patent_title] => APPARATUSES AND METHODS FOR SAMPLE RATE ADJUSTMENT [patent_app_type] => utility [patent_app_number] => 17/650622 [patent_app_country] => US [patent_app_date] => 2022-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9776 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17650622 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/650622
Apparatuses and methods for sample rate adjustment Feb 9, 2022 Issued
Array ( [id] => 17833365 [patent_doc_number] => 20220270669 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-25 [patent_title] => REFRESH CIRCUIT AND MEMORY [patent_app_type] => utility [patent_app_number] => 17/650516 [patent_app_country] => US [patent_app_date] => 2022-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4873 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17650516 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/650516
Refresh circuit and memory Feb 8, 2022 Issued
Array ( [id] => 17613908 [patent_doc_number] => 20220156188 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-19 [patent_title] => BLOCK FAMILY COMBINATION AND VOLTAGE BIN SELECTION [patent_app_type] => utility [patent_app_number] => 17/667326 [patent_app_country] => US [patent_app_date] => 2022-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12428 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17667326 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/667326
Block family combination and voltage bin selection Feb 7, 2022 Issued
Array ( [id] => 19123391 [patent_doc_number] => 11967385 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-23 [patent_title] => Semiconductor storage device and memory system [patent_app_type] => utility [patent_app_number] => 17/665391 [patent_app_country] => US [patent_app_date] => 2022-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 34 [patent_no_of_words] => 25428 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17665391 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/665391
Semiconductor storage device and memory system Feb 3, 2022 Issued
Array ( [id] => 17599702 [patent_doc_number] => 20220149276 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-12 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/584868 [patent_app_country] => US [patent_app_date] => 2022-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7126 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17584868 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/584868
Semiconductor memory device Jan 25, 2022 Issued
Array ( [id] => 18240522 [patent_doc_number] => 20230072833 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-09 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/578803 [patent_app_country] => US [patent_app_date] => 2022-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12667 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17578803 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/578803
SEMICONDUCTOR MEMORY DEVICE Jan 18, 2022 Abandoned
Array ( [id] => 18500274 [patent_doc_number] => 20230223059 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-13 [patent_title] => APPARATUSES AND METHODS INCLUDING DICE LATCHES IN A SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/575378 [patent_app_country] => US [patent_app_date] => 2022-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10776 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17575378 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/575378
Apparatuses and methods including dice latches in a semiconductor device Jan 12, 2022 Issued
Array ( [id] => 19376442 [patent_doc_number] => 12068020 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-20 [patent_title] => Dynamic memory with sustainable storage architecture and clean up circuit [patent_app_type] => utility [patent_app_number] => 17/574494 [patent_app_country] => US [patent_app_date] => 2022-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 35 [patent_no_of_words] => 11974 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17574494 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/574494
Dynamic memory with sustainable storage architecture and clean up circuit Jan 11, 2022 Issued
Array ( [id] => 17899124 [patent_doc_number] => 20220308786 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-29 [patent_title] => METHOD AND APPARATUS FOR DETERMINING MISMATCH OF SENSE AMPLIFIER, STORAG MEDIUM, AND ELECTRONIC EQUIPMENT [patent_app_type] => utility [patent_app_number] => 17/647472 [patent_app_country] => US [patent_app_date] => 2022-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9173 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17647472 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/647472
Method and apparatus for determining mismatch of sense amplifier, storage medium, and electronic equipment Jan 9, 2022 Issued
Array ( [id] => 19314199 [patent_doc_number] => 12040023 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-16 [patent_title] => Writing method of flash memory and memory storage device [patent_app_type] => utility [patent_app_number] => 17/563095 [patent_app_country] => US [patent_app_date] => 2021-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 2794 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17563095 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/563095
Writing method of flash memory and memory storage device Dec 27, 2021 Issued
Array ( [id] => 18195271 [patent_doc_number] => 20230048790 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-16 [patent_title] => MEMORY DEVICE AND METHOD OF OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 17/557342 [patent_app_country] => US [patent_app_date] => 2021-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11465 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17557342 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/557342
Memory device and method of operating the same Dec 20, 2021 Issued
Array ( [id] => 18455859 [patent_doc_number] => 20230197140 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-22 [patent_title] => MEMORY DEVICE CONTROL SCHEMES, AND ASSOCIATED METHODS, DEVICES, AND SYSTEMS [patent_app_type] => utility [patent_app_number] => 17/645253 [patent_app_country] => US [patent_app_date] => 2021-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8912 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17645253 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/645253
Memory device control schemes, and associated methods, devices, and systems Dec 19, 2021 Issued
Array ( [id] => 19062936 [patent_doc_number] => 11942181 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-26 [patent_title] => Semiconductor device including internal transmission path and stacked semiconductor device using the same [patent_app_type] => utility [patent_app_number] => 17/554226 [patent_app_country] => US [patent_app_date] => 2021-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 14126 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17554226 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/554226
Semiconductor device including internal transmission path and stacked semiconductor device using the same Dec 16, 2021 Issued
Array ( [id] => 18457229 [patent_doc_number] => 20230198511 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-22 [patent_title] => SPLIT PULSE WIDTH MODULATION TO REDUCE CROSSBAR ARRAY INTEGRATION TIME [patent_app_type] => utility [patent_app_number] => 17/555178 [patent_app_country] => US [patent_app_date] => 2021-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10368 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17555178 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/555178
Split pulse width modulation to reduce crossbar array integration time Dec 16, 2021 Issued
Menu