Search

Bot L. Ledynh

Examiner (ID: 14473, Phone: (571)272-2231 , Office: P/2858 )

Most Active Art Unit
2858
Art Unit(s)
2831, 2858, 2899, 2862, 2103
Total Applications
2040
Issued Applications
1805
Pending Applications
55
Abandoned Applications
180

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16987811 [patent_doc_number] => 11074990 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-27 [patent_title] => Nonvolatile memory device including a plurality of input/output units and an operating method thereof [patent_app_type] => utility [patent_app_number] => 16/701205 [patent_app_country] => US [patent_app_date] => 2019-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 6838 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16701205 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/701205
Nonvolatile memory device including a plurality of input/output units and an operating method thereof Dec 2, 2019 Issued
Array ( [id] => 17061781 [patent_doc_number] => 11106381 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-31 [patent_title] => Automated seamless migration of logical storage devices [patent_app_type] => utility [patent_app_number] => 16/697393 [patent_app_country] => US [patent_app_date] => 2019-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 13160 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16697393 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/697393
Automated seamless migration of logical storage devices Nov 26, 2019 Issued
Array ( [id] => 16543364 [patent_doc_number] => 20200409779 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-31 [patent_title] => Use Of Error Correction-Based Metric For Identifying Poorly Performing Data Storage Devices [patent_app_type] => utility [patent_app_number] => 16/688992 [patent_app_country] => US [patent_app_date] => 2019-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12866 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16688992 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/688992
Use of error correction-based metric for identifying poorly performing data storage devices Nov 18, 2019 Issued
Array ( [id] => 15902961 [patent_doc_number] => 20200151000 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-14 [patent_title] => CONFIGURABLE INTEGRATED CIRCUIT TO SUPPORT NEW CAPABILITY [patent_app_type] => utility [patent_app_number] => 16/681471 [patent_app_country] => US [patent_app_date] => 2019-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5476 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16681471 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/681471
Configurable integrated circuit to support new capability Nov 11, 2019 Issued
Array ( [id] => 16826268 [patent_doc_number] => 20210141561 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-13 [patent_title] => BACKGROUND OPERATION SELECTION BASED ON HOST IDLE TIME [patent_app_type] => utility [patent_app_number] => 16/678850 [patent_app_country] => US [patent_app_date] => 2019-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6179 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16678850 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/678850
Background operation selection based on host idle time Nov 7, 2019 Issued
Array ( [id] => 15594633 [patent_doc_number] => 20200073851 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-05 [patent_title] => SCALABLE 2.5D INTERFACE CIRCUITRY [patent_app_type] => utility [patent_app_number] => 16/674138 [patent_app_country] => US [patent_app_date] => 2019-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6500 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16674138 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/674138
Scalable 2.5D interface circuitry Nov 4, 2019 Issued
Array ( [id] => 15561705 [patent_doc_number] => 20200065264 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-27 [patent_title] => Data Processing Method and System [patent_app_type] => utility [patent_app_number] => 16/673320 [patent_app_country] => US [patent_app_date] => 2019-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22444 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16673320 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/673320
Non-volatile memory (NVM) express (NVMe) data processing method and system Nov 3, 2019 Issued
Array ( [id] => 15459321 [patent_doc_number] => 20200042485 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-06 [patent_title] => ASYNCHRONOUS MAPPING OF HOT-PLUGGED DEVICE ASSOCIATED WITH VIRTUAL MACHINE [patent_app_type] => utility [patent_app_number] => 16/653222 [patent_app_country] => US [patent_app_date] => 2019-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4404 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16653222 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/653222
Asynchronous mapping of hot-plugged device associated with virtual machine Oct 14, 2019 Issued
Array ( [id] => 15700665 [patent_doc_number] => 10606508 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-03-31 [patent_title] => Storage system [patent_app_type] => utility [patent_app_number] => 16/561856 [patent_app_country] => US [patent_app_date] => 2019-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 5088 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16561856 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/561856
Storage system Sep 4, 2019 Issued
Array ( [id] => 18734771 [patent_doc_number] => 11803502 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-31 [patent_title] => Setting apparatus and setting method [patent_app_type] => utility [patent_app_number] => 17/631966 [patent_app_country] => US [patent_app_date] => 2019-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 31 [patent_no_of_words] => 60519 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17631966 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/631966
Setting apparatus and setting method Aug 7, 2019 Issued
Array ( [id] => 17046848 [patent_doc_number] => 11100029 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-24 [patent_title] => Interface bridge between integrated circuit die [patent_app_type] => utility [patent_app_number] => 16/536147 [patent_app_country] => US [patent_app_date] => 2019-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 7289 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16536147 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/536147
Interface bridge between integrated circuit die Aug 7, 2019 Issued
Array ( [id] => 16737738 [patent_doc_number] => 10963390 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-30 [patent_title] => Memory-adaptive processing method for convolutional neural network and system thereof [patent_app_type] => utility [patent_app_number] => 16/533872 [patent_app_country] => US [patent_app_date] => 2019-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 5104 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16533872 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/533872
Memory-adaptive processing method for convolutional neural network and system thereof Aug 6, 2019 Issued
Array ( [id] => 16972443 [patent_doc_number] => 11068415 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-20 [patent_title] => Using insertion points to determine locations in a cache list at which to move processed tracks [patent_app_type] => utility [patent_app_number] => 16/534705 [patent_app_country] => US [patent_app_date] => 2019-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 6704 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16534705 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/534705
Using insertion points to determine locations in a cache list at which to move processed tracks Aug 6, 2019 Issued
Array ( [id] => 17092685 [patent_doc_number] => 11120879 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-14 [patent_title] => Adjustment of a voltage corresponding to an erase distribution of a memory sub-system in accordance with a selected rule [patent_app_type] => utility [patent_app_number] => 16/534097 [patent_app_country] => US [patent_app_date] => 2019-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 19297 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16534097 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/534097
Adjustment of a voltage corresponding to an erase distribution of a memory sub-system in accordance with a selected rule Aug 6, 2019 Issued
Array ( [id] => 16095143 [patent_doc_number] => 20200201558 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-25 [patent_title] => SYSTEM INCLUDING DATA STORAGE DEVICE AND METHOD OF CONTROLLING DISCARD OPERATION IN THE SAME [patent_app_type] => utility [patent_app_number] => 16/533256 [patent_app_country] => US [patent_app_date] => 2019-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8166 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16533256 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/533256
System including data storage device and method of controlling discard operation in the same Aug 5, 2019 Issued
Array ( [id] => 15887213 [patent_doc_number] => 10649951 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-12 [patent_title] => Monolithically integrated system on chip for silicon photonics [patent_app_type] => utility [patent_app_number] => 16/529473 [patent_app_country] => US [patent_app_date] => 2019-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 9226 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 376 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16529473 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/529473
Monolithically integrated system on chip for silicon photonics Jul 31, 2019 Issued
Array ( [id] => 15089941 [patent_doc_number] => 20190339781 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-07 [patent_title] => Device and Method for Outputting A Series of Haptic Effects Defined in a Timeline Effect Definition [patent_app_type] => utility [patent_app_number] => 16/515170 [patent_app_country] => US [patent_app_date] => 2019-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11065 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16515170 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/515170
Device and method for outputting a series of haptic effects defined in a timeline effect definition Jul 17, 2019 Issued
Array ( [id] => 17151149 [patent_doc_number] => 11144226 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-10-12 [patent_title] => Intelligent path selection and load balancing [patent_app_type] => utility [patent_app_number] => 16/459166 [patent_app_country] => US [patent_app_date] => 2019-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 40 [patent_no_of_words] => 13378 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16459166 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/459166
Intelligent path selection and load balancing Jun 30, 2019 Issued
Array ( [id] => 17824555 [patent_doc_number] => 11429503 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-08-30 [patent_title] => Auto-detection of interconnect hangs in integrated circuits [patent_app_type] => utility [patent_app_number] => 16/456902 [patent_app_country] => US [patent_app_date] => 2019-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4017 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16456902 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/456902
Auto-detection of interconnect hangs in integrated circuits Jun 27, 2019 Issued
Array ( [id] => 16501530 [patent_doc_number] => 10866915 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-15 [patent_title] => Method for increasing the compatibility of displayport [patent_app_type] => utility [patent_app_number] => 16/457703 [patent_app_country] => US [patent_app_date] => 2019-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4835 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 306 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16457703 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/457703
Method for increasing the compatibility of displayport Jun 27, 2019 Issued
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