Search

Bradley Duffy

Examiner (ID: 10706, Phone: (571)272-9935 , Office: P/1643 )

Most Active Art Unit
1643
Art Unit(s)
1643
Total Applications
1084
Issued Applications
492
Pending Applications
120
Abandoned Applications
488

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20324800 [patent_doc_number] => 20250336888 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-30 [patent_title] => METHOD OF MAKING A FAN-OUT SEMICONDUCTOR ASSEMBLY WITH AN INTERMEDIATE CARRIER [patent_app_type] => utility [patent_app_number] => 19/259621 [patent_app_country] => US [patent_app_date] => 2025-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10919 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19259621 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/259621
METHOD OF MAKING A FAN-OUT SEMICONDUCTOR ASSEMBLY WITH AN INTERMEDIATE CARRIER Jul 2, 2025 Pending
Array ( [id] => 19727160 [patent_doc_number] => 20250029911 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-23 [patent_title] => MANUFACTURING METHOD OF SEMICONDUCTOR SUBSTRATE [patent_app_type] => utility [patent_app_number] => 18/909899 [patent_app_country] => US [patent_app_date] => 2024-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9438 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18909899 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/909899
MANUFACTURING METHOD OF SEMICONDUCTOR SUBSTRATE Oct 7, 2024 Abandoned
Array ( [id] => 19935129 [patent_doc_number] => 12308337 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2025-05-20 [patent_title] => Power semiconductor apparatus and bonding method thereof [patent_app_type] => utility [patent_app_number] => 18/882721 [patent_app_country] => US [patent_app_date] => 2024-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 0 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18882721 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/882721
Power semiconductor apparatus and bonding method thereof Sep 10, 2024 Issued
Array ( [id] => 20283753 [patent_doc_number] => 20250308995 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-02 [patent_title] => SEMICONDUCTOR DEVICE INCLUDING METAL LINES HAVING MULTI-LAYER STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/820847 [patent_app_country] => US [patent_app_date] => 2024-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18820847 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/820847
SEMICONDUCTOR DEVICE INCLUDING METAL LINES HAVING MULTI-LAYER STRUCTURE Aug 29, 2024 Pending
Array ( [id] => 20418447 [patent_doc_number] => 12501753 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-16 [patent_title] => Light-emitting device [patent_app_type] => utility [patent_app_number] => 18/773873 [patent_app_country] => US [patent_app_date] => 2024-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 17 [patent_no_of_words] => 6686 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18773873 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/773873
Light-emitting device Jul 15, 2024 Issued
Array ( [id] => 20720237 [patent_doc_number] => 12635509 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-19 [patent_title] => Package structure [patent_app_type] => utility [patent_app_number] => 18/769153 [patent_app_country] => US [patent_app_date] => 2024-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 42 [patent_no_of_words] => 2036 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18769153 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/769153
Package structure Jul 9, 2024 Issued
Array ( [id] => 20111586 [patent_doc_number] => 12362322 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-15 [patent_title] => Method of making a fan-out semiconductor assembly with an intermediate carrier [patent_app_type] => utility [patent_app_number] => 18/748007 [patent_app_country] => US [patent_app_date] => 2024-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 53 [patent_no_of_words] => 10798 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18748007 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/748007
Method of making a fan-out semiconductor assembly with an intermediate carrier Jun 18, 2024 Issued
Array ( [id] => 19484178 [patent_doc_number] => 20240332220 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => INTERPOSER INCLUDING A COPPER EDGE SEAL RING STRUCTURE AND METHODS OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/742278 [patent_app_country] => US [patent_app_date] => 2024-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9187 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18742278 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/742278
Interposer including a copper edge seal ring structure and methods of forming the same Jun 12, 2024 Issued
Array ( [id] => 19821108 [patent_doc_number] => 20250079315 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-06 [patent_title] => SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/677434 [patent_app_country] => US [patent_app_date] => 2024-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2373 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18677434 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/677434
SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME May 28, 2024 Pending
Array ( [id] => 19452734 [patent_doc_number] => 20240312864 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-19 [patent_title] => PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/676343 [patent_app_country] => US [patent_app_date] => 2024-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11814 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18676343 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/676343
PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF May 27, 2024 Issued
Array ( [id] => 20291366 [patent_doc_number] => 20250316609 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-09 [patent_title] => METHOD FOR AUTOMATICALLY GENERATING CHIP IDENTIFIERS FOR SEMICONDUCTOR DIES IN STACKED STRUCTURE, SEMICONDUCTOR DEVICE, AND MEMORY DEVICE USING THE SAME [patent_app_type] => utility [patent_app_number] => 18/664617 [patent_app_country] => US [patent_app_date] => 2024-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3552 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18664617 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/664617
METHOD FOR AUTOMATICALLY GENERATING CHIP IDENTIFIERS FOR SEMICONDUCTOR DIES IN STACKED STRUCTURE, SEMICONDUCTOR DEVICE, AND MEMORY DEVICE USING THE SAME May 14, 2024 Pending
Array ( [id] => 19943593 [patent_doc_number] => 12315729 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2025-05-27 [patent_title] => Laser-based processing for semiconductor wafers [patent_app_type] => utility [patent_app_number] => 18/661994 [patent_app_country] => US [patent_app_date] => 2024-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 22 [patent_no_of_words] => 11465 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18661994 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/661994
Laser-based processing for semiconductor wafers May 12, 2024 Issued
Array ( [id] => 19421112 [patent_doc_number] => 20240297236 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-05 [patent_title] => METHODS OF REDUCING CAPACITANCE IN FIELD-EFFECT TRANSISTORS [patent_app_type] => utility [patent_app_number] => 18/648069 [patent_app_country] => US [patent_app_date] => 2024-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9638 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18648069 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/648069
Methods of reducing capacitance in field-effect transistors Apr 25, 2024 Issued
Array ( [id] => 20734848 [patent_doc_number] => 12642116 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-26 [patent_title] => Package substrate [patent_app_type] => utility [patent_app_number] => 18/645381 [patent_app_country] => US [patent_app_date] => 2024-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 28 [patent_no_of_words] => 4325 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18645381 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/645381
Package substrate Apr 24, 2024 Issued
Array ( [id] => 20259002 [patent_doc_number] => 12431365 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-30 [patent_title] => Bump structure and method of making the same [patent_app_type] => utility [patent_app_number] => 18/642173 [patent_app_country] => US [patent_app_date] => 2024-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 37 [patent_no_of_words] => 3505 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18642173 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/642173
Bump structure and method of making the same Apr 21, 2024 Issued
Array ( [id] => 19712581 [patent_doc_number] => 20250022723 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-16 [patent_title] => ELECTRONIC PACKAGE AND FABRICATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/640838 [patent_app_country] => US [patent_app_date] => 2024-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5103 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18640838 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/640838
Electronic package and fabricating method thereof Apr 18, 2024 Issued
Array ( [id] => 19364269 [patent_doc_number] => 20240266303 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-08 [patent_title] => CHIPLET INTERPOSER [patent_app_type] => utility [patent_app_number] => 18/635315 [patent_app_country] => US [patent_app_date] => 2024-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13162 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18635315 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/635315
Chiplet interposer Apr 14, 2024 Issued
Array ( [id] => 20291365 [patent_doc_number] => 20250316608 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-09 [patent_title] => METHOD FOR AUTOMATICALLY GENERATING CHIP IDENTIFIERS FOR SEMICONDUCTOR DIES IN STACKED STRUCTURE, SEMICONDUCTOR DEVICE, AND MEMORY DEVICE USING THE SAME [patent_app_type] => utility [patent_app_number] => 18/630200 [patent_app_country] => US [patent_app_date] => 2024-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3724 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18630200 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/630200
METHOD FOR AUTOMATICALLY GENERATING CHIP IDENTIFIERS FOR SEMICONDUCTOR DIES IN STACKED STRUCTURE, SEMICONDUCTOR DEVICE, AND MEMORY DEVICE USING THE SAME Apr 8, 2024 Pending
Array ( [id] => 20291381 [patent_doc_number] => 20250316624 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-09 [patent_title] => SEMICONDUCTOR PACKAGES AND METHODS OF FABRICATING THEREOF [patent_app_type] => utility [patent_app_number] => 18/626988 [patent_app_country] => US [patent_app_date] => 2024-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1190 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18626988 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/626988
SEMICONDUCTOR PACKAGES AND METHODS OF FABRICATING THEREOF Apr 3, 2024 Pending
Array ( [id] => 19335569 [patent_doc_number] => 20240249999 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-25 [patent_title] => Packaged Semiconductor Device Including Liquid-Cooled Lid and Methods of Forming the Same [patent_app_type] => utility [patent_app_number] => 18/605947 [patent_app_country] => US [patent_app_date] => 2024-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12638 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18605947 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/605947
Packaged semiconductor device including liquid-cooled lid and methods of forming the same Mar 14, 2024 Issued
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