
Bradley Smith
Examiner (ID: 18376)
| Most Active Art Unit | 2817 |
| Art Unit(s) | 2891, 2894, 2824, 2818, 2817, 2829 |
| Total Applications | 1766 |
| Issued Applications | 1463 |
| Pending Applications | 117 |
| Abandoned Applications | 227 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 13558867
[patent_doc_number] => 20180330981
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-11-15
[patent_title] => Method for Thinning Substrates
[patent_app_type] => utility
[patent_app_number] => 16/032862
[patent_app_country] => US
[patent_app_date] => 2018-07-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 16289
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -21
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16032862
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/032862 | Method for Thinning Substrates | Jul 10, 2018 | Abandoned |
Array
(
[id] => 16180294
[patent_doc_number] => 20200227263
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-07-16
[patent_title] => Device Substrate With High Thermal Conductivity And Method Of Manufacturing The Same
[patent_app_type] => utility
[patent_app_number] => 16/626154
[patent_app_country] => US
[patent_app_date] => 2018-07-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7801
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -10
[patent_words_short_claim] => 74
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16626154
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/626154 | Device substrate with high thermal conductivity and method of manufacturing the same | Jul 9, 2018 | Issued |
Array
(
[id] => 15108675
[patent_doc_number] => 10475668
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-11-12
[patent_title] => Apparatus and method for processing a semiconductor substrate
[patent_app_type] => utility
[patent_app_number] => 16/021619
[patent_app_country] => US
[patent_app_date] => 2018-06-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 12
[patent_no_of_words] => 5642
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 240
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16021619
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/021619 | Apparatus and method for processing a semiconductor substrate | Jun 27, 2018 | Issued |
Array
(
[id] => 15274301
[patent_doc_number] => 20190385885
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-12-19
[patent_title] => MULTI-LAYER TETHERS FOR MICRO-TRANSFER PRINTING
[patent_app_type] => utility
[patent_app_number] => 16/008945
[patent_app_country] => US
[patent_app_date] => 2018-06-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6908
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -25
[patent_words_short_claim] => 58
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16008945
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/008945 | Multi-layer tethers for micro-transfer printing | Jun 13, 2018 | Issued |
Array
(
[id] => 13629545
[patent_doc_number] => 20180366325
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-12-20
[patent_title] => METHODS OF EXFOLIATING SINGLE CRYSTAL MATERIALS
[patent_app_type] => utility
[patent_app_number] => 16/009037
[patent_app_country] => US
[patent_app_date] => 2018-06-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9006
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -10
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16009037
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/009037 | METHODS OF EXFOLIATING SINGLE CRYSTAL MATERIALS | Jun 13, 2018 | Abandoned |
Array
(
[id] => 13740483
[patent_doc_number] => 20180374711
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-12-27
[patent_title] => METHOD FOR MAKING NANOSTRUCTURES
[patent_app_type] => utility
[patent_app_number] => 16/008216
[patent_app_country] => US
[patent_app_date] => 2018-06-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5469
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -12
[patent_words_short_claim] => 285
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16008216
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/008216 | Method for making nanostructures | Jun 13, 2018 | Issued |
Array
(
[id] => 18175159
[patent_doc_number] => 11574876
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-02-07
[patent_title] => Microchip charge patterning
[patent_app_type] => utility
[patent_app_number] => 16/008961
[patent_app_country] => US
[patent_app_date] => 2018-06-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 16
[patent_no_of_words] => 2497
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 123
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16008961
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/008961 | Microchip charge patterning | Jun 13, 2018 | Issued |
Array
(
[id] => 15611735
[patent_doc_number] => 10586940
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-03-10
[patent_title] => Organic light emitting diode substrate and preparation method thereof, and display panel
[patent_app_type] => utility
[patent_app_number] => 16/007188
[patent_app_country] => US
[patent_app_date] => 2018-06-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 10
[patent_no_of_words] => 6466
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 92
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16007188
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/007188 | Organic light emitting diode substrate and preparation method thereof, and display panel | Jun 12, 2018 | Issued |
Array
(
[id] => 15841383
[patent_doc_number] => 20200135974
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-04-30
[patent_title] => III-NITRIDE DOWN-CONVERSION NANOMATERIAL FOR WHITE LEDS
[patent_app_type] => utility
[patent_app_number] => 16/619808
[patent_app_country] => US
[patent_app_date] => 2018-06-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2885
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16619808
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/619808 | III-nitride down-conversion nanomaterial for white LEDs | Jun 7, 2018 | Issued |
Array
(
[id] => 16574994
[patent_doc_number] => 10896922
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-01-19
[patent_title] => Imaging apparatus, imaging system, moving object, and method for manufacturing imaging apparatus
[patent_app_type] => utility
[patent_app_number] => 15/996313
[patent_app_country] => US
[patent_app_date] => 2018-06-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 17
[patent_no_of_words] => 9119
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 123
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15996313
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/996313 | Imaging apparatus, imaging system, moving object, and method for manufacturing imaging apparatus | May 31, 2018 | Issued |
Array
(
[id] => 15906033
[patent_doc_number] => 20200152537
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-05-14
[patent_title] => SEMICONDUCTOR APPARATUS
[patent_app_type] => utility
[patent_app_number] => 16/617307
[patent_app_country] => US
[patent_app_date] => 2018-05-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8442
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 51
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16617307
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/617307 | Semiconductor apparatus | May 27, 2018 | Issued |
Array
(
[id] => 14938277
[patent_doc_number] => 20190304777
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-10-03
[patent_title] => METHOD FOR FORMING HARD MASK
[patent_app_type] => utility
[patent_app_number] => 15/964031
[patent_app_country] => US
[patent_app_date] => 2018-04-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2817
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -13
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15964031
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/964031 | METHOD FOR FORMING HARD MASK | Apr 25, 2018 | Abandoned |
Array
(
[id] => 13392977
[patent_doc_number] => 20180248031
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-08-30
[patent_title] => METHOD FOR MANUFACTURING THIN FILM TRANSISTOR SUBSTRATE
[patent_app_type] => utility
[patent_app_number] => 15/964026
[patent_app_country] => US
[patent_app_date] => 2018-04-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8797
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -8
[patent_words_short_claim] => 128
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15964026
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/964026 | Method for manufacturing thin film transistor substrate | Apr 25, 2018 | Issued |
Array
(
[id] => 16249494
[patent_doc_number] => 10748869
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-08-18
[patent_title] => Protective layer for contact pads in fan-out interconnect structure and method of forming same
[patent_app_type] => utility
[patent_app_number] => 15/938451
[patent_app_country] => US
[patent_app_date] => 2018-03-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 20
[patent_no_of_words] => 4704
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 167
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15938451
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/938451 | Protective layer for contact pads in fan-out interconnect structure and method of forming same | Mar 27, 2018 | Issued |
Array
(
[id] => 14690047
[patent_doc_number] => 20190244139
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-08-08
[patent_title] => USING META-LEARNING FOR AUTOMATIC GRADIENT-BASED HYPERPARAMETER OPTIMIZATION FOR MACHINE LEARNING AND DEEP LEARNING MODELS
[patent_app_type] => utility
[patent_app_number] => 15/914883
[patent_app_country] => US
[patent_app_date] => 2018-03-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10755
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 71
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15914883
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/914883 | USING META-LEARNING FOR AUTOMATIC GRADIENT-BASED HYPERPARAMETER OPTIMIZATION FOR MACHINE LEARNING AND DEEP LEARNING MODELS | Mar 6, 2018 | Abandoned |
Array
(
[id] => 16238745
[patent_doc_number] => 20200255979
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-08-13
[patent_title] => GALLIUM NITRIDE CRYSTAL SUBSTRATE
[patent_app_type] => utility
[patent_app_number] => 16/651716
[patent_app_country] => US
[patent_app_date] => 2018-02-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 19127
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -2
[patent_words_short_claim] => 186
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16651716
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/651716 | Gallium nitride crystal substrate | Feb 22, 2018 | Issued |
Array
(
[id] => 14267753
[patent_doc_number] => 10283448
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-05-07
[patent_title] => Multiple metal layer semiconductor device and low temperature stacking method of fabricating the same
[patent_app_type] => utility
[patent_app_number] => 15/887142
[patent_app_country] => US
[patent_app_date] => 2018-02-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 24
[patent_no_of_words] => 4623
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 177
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15887142
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/887142 | Multiple metal layer semiconductor device and low temperature stacking method of fabricating the same | Feb 1, 2018 | Issued |
Array
(
[id] => 14658721
[patent_doc_number] => 20190236489
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-08-01
[patent_title] => METHOD AND SYSTEM FOR INDUSTRIAL PARTS SEARCH, HARMONIZATION, AND RATIONALIZATION THROUGH DIGITAL TWIN TECHNOLOGY
[patent_app_type] => utility
[patent_app_number] => 15/883895
[patent_app_country] => US
[patent_app_date] => 2018-01-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6324
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 130
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15883895
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/883895 | METHOD AND SYSTEM FOR INDUSTRIAL PARTS SEARCH, HARMONIZATION, AND RATIONALIZATION THROUGH DIGITAL TWIN TECHNOLOGY | Jan 29, 2018 | Abandoned |
Array
(
[id] => 15608043
[patent_doc_number] => 10585074
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-03-10
[patent_title] => Method of fabricating a MEMS and/or NEMS structure comprising at least two elements suspended from a support at different distances from said support
[patent_app_type] => utility
[patent_app_number] => 15/873136
[patent_app_country] => US
[patent_app_date] => 2018-01-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 33
[patent_no_of_words] => 3716
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 202
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15873136
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/873136 | Method of fabricating a MEMS and/or NEMS structure comprising at least two elements suspended from a support at different distances from said support | Jan 16, 2018 | Issued |
Array
(
[id] => 13755285
[patent_doc_number] => 10170597
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-01-01
[patent_title] => Method for forming flash memory unit
[patent_app_type] => utility
[patent_app_number] => 15/872998
[patent_app_country] => US
[patent_app_date] => 2018-01-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 10
[patent_no_of_words] => 5607
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 260
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15872998
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/872998 | Method for forming flash memory unit | Jan 16, 2018 | Issued |