Search

Bradley Smith

Examiner (ID: 12315, Phone: (571)272-1884 , Office: P/2817 )

Most Active Art Unit
2817
Art Unit(s)
2829, 2894, 2818, 2817, 2824, 2891
Total Applications
1806
Issued Applications
1488
Pending Applications
116
Abandoned Applications
231

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15217951 [patent_doc_number] => 20190371662 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-05 [patent_title] => Nucleation-Free Gap Fill ALD Process [patent_app_type] => utility [patent_app_number] => 16/467669 [patent_app_country] => US [patent_app_date] => 2017-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7487 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16467669 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/467669
Nucleation-free gap fill ALD process Nov 28, 2017 Issued
Array ( [id] => 14859607 [patent_doc_number] => 10418540 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-17 [patent_title] => Adjustment of qubit frequency through annealing [patent_app_type] => utility [patent_app_number] => 15/824438 [patent_app_country] => US [patent_app_date] => 2017-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 4589 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15824438 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/824438
Adjustment of qubit frequency through annealing Nov 27, 2017 Issued
Array ( [id] => 14526333 [patent_doc_number] => 10340438 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-02 [patent_title] => Laser annealing qubits for optimized frequency allocation [patent_app_type] => utility [patent_app_number] => 15/823728 [patent_app_country] => US [patent_app_date] => 2017-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6834 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15823728 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/823728
Laser annealing qubits for optimized frequency allocation Nov 27, 2017 Issued
Array ( [id] => 13378693 [patent_doc_number] => 20180240888 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-23 [patent_title] => METHOD FOR MANUFACTURING A TRANSISTOR AND METHOD FOR MANUFACTURING A RING OSCILLATOR USING THE SAME [patent_app_type] => utility [patent_app_number] => 15/824373 [patent_app_country] => US [patent_app_date] => 2017-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4063 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15824373 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/824373
Method for manufacturing a transistor and method for manufacturing a ring oscillator using the same Nov 27, 2017 Issued
Array ( [id] => 15611269 [patent_doc_number] => 10586704 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-10 [patent_title] => Wafer processing method [patent_app_type] => utility [patent_app_number] => 15/824365 [patent_app_country] => US [patent_app_date] => 2017-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4344 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15824365 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/824365
Wafer processing method Nov 27, 2017 Issued
Array ( [id] => 13921845 [patent_doc_number] => 10205048 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-02-12 [patent_title] => Method for manufacturing a light emitting diode chip [patent_app_type] => utility [patent_app_number] => 15/822227 [patent_app_country] => US [patent_app_date] => 2017-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 2389 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15822227 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/822227
Method for manufacturing a light emitting diode chip Nov 26, 2017 Issued
Array ( [id] => 16280117 [patent_doc_number] => 10763157 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-01 [patent_title] => Method for manufacturing SOI wafer [patent_app_type] => utility [patent_app_number] => 16/465879 [patent_app_country] => US [patent_app_date] => 2017-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 4270 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16465879 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/465879
Method for manufacturing SOI wafer Nov 26, 2017 Issued
Array ( [id] => 12243493 [patent_doc_number] => 20180076356 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-15 [patent_title] => 'VERTICAL TOPOLOGY LIGHT EMITTING DEVICE' [patent_app_type] => utility [patent_app_number] => 15/813396 [patent_app_country] => US [patent_app_date] => 2017-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 6717 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15813396 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/813396
Vertical topology light emitting device Nov 14, 2017 Issued
Array ( [id] => 13070975 [patent_doc_number] => 10056272 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-08-21 [patent_title] => Gas-controlled bonding platform for edge defect reduction during wafer bonding [patent_app_type] => utility [patent_app_number] => 15/811738 [patent_app_country] => US [patent_app_date] => 2017-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4354 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 259 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15811738 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/811738
Gas-controlled bonding platform for edge defect reduction during wafer bonding Nov 13, 2017 Issued
Array ( [id] => 13132353 [patent_doc_number] => 10084116 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-09-25 [patent_title] => Light emitting device and light emitting device package [patent_app_type] => utility [patent_app_number] => 15/804021 [patent_app_country] => US [patent_app_date] => 2017-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 24 [patent_no_of_words] => 9176 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15804021 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/804021
Light emitting device and light emitting device package Nov 5, 2017 Issued
Array ( [id] => 13921705 [patent_doc_number] => 10204977 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-12 [patent_title] => Making electrical components in handle wafers of integrated circuit packages [patent_app_type] => utility [patent_app_number] => 15/804847 [patent_app_country] => US [patent_app_date] => 2017-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 4822 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 378 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15804847 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/804847
Making electrical components in handle wafers of integrated circuit packages Nov 5, 2017 Issued
Array ( [id] => 12778588 [patent_doc_number] => 20180151364 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-31 [patent_title] => METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 15/789273 [patent_app_country] => US [patent_app_date] => 2017-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2339 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15789273 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/789273
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE Oct 19, 2017 Abandoned
Array ( [id] => 14221293 [patent_doc_number] => 20190123031 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-25 [patent_title] => ELASTOMERIC LAYER FABRICATION FOR LIGHT EMITTING DIODES [patent_app_type] => utility [patent_app_number] => 15/789275 [patent_app_country] => US [patent_app_date] => 2017-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6517 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15789275 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/789275
Elastomeric layer fabrication for light emitting diodes Oct 19, 2017 Issued
Array ( [id] => 13963285 [patent_doc_number] => 20190057987 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-21 [patent_title] => FORMING METHOD OF VIA HOLE AND MANUFACTURING METHOD OF PIXEL STRUCTURE [patent_app_type] => utility [patent_app_number] => 15/788813 [patent_app_country] => US [patent_app_date] => 2017-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5105 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15788813 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/788813
Forming method of via hole and manufacturing method of pixel structure Oct 19, 2017 Issued
Array ( [id] => 14163885 [patent_doc_number] => 20190109045 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-11 [patent_title] => METHODS OF FORMING CONDUCTIVE CONTACT STRUCTURES TO SEMICONDUCTOR DEVICES AND THE RESULTING STRUCTURES [patent_app_type] => utility [patent_app_number] => 15/728632 [patent_app_country] => US [patent_app_date] => 2017-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7395 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15728632 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/728632
Methods of forming conductive contact structures to semiconductor devices and the resulting structures Oct 9, 2017 Issued
Array ( [id] => 15250631 [patent_doc_number] => 10510845 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-17 [patent_title] => Method for manufacturing electrode of semiconductor device [patent_app_type] => utility [patent_app_number] => 15/728160 [patent_app_country] => US [patent_app_date] => 2017-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 4497 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15728160 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/728160
Method for manufacturing electrode of semiconductor device Oct 8, 2017 Issued
Array ( [id] => 12693190 [patent_doc_number] => 20180122896 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-03 [patent_title] => NOVEL CHANNEL STOP IMP FOR THE FINFET DEVICE [patent_app_type] => utility [patent_app_number] => 15/728184 [patent_app_country] => US [patent_app_date] => 2017-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2964 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15728184 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/728184
Channel stop imp for the FinFET device Oct 8, 2017 Issued
Array ( [id] => 12760255 [patent_doc_number] => 20180145253 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-24 [patent_title] => Method of Forming Resistive Random Access Memory (RRAM) Cells [patent_app_type] => utility [patent_app_number] => 15/727776 [patent_app_country] => US [patent_app_date] => 2017-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3118 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15727776 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/727776
Method of Forming Resistive Random Access Memory (RRAM) Cells Oct 8, 2017 Abandoned
Array ( [id] => 17152450 [patent_doc_number] => 11145541 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-10-12 [patent_title] => Conductive via and metal line end fabrication and structures resulting therefrom [patent_app_type] => utility [patent_app_number] => 16/637930 [patent_app_country] => US [patent_app_date] => 2017-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 11620 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16637930 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/637930
Conductive via and metal line end fabrication and structures resulting therefrom Sep 29, 2017 Issued
Array ( [id] => 13111981 [patent_doc_number] => 10074648 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-09-11 [patent_title] => Method of manufacturing semiconductor device [patent_app_type] => utility [patent_app_number] => 15/718749 [patent_app_country] => US [patent_app_date] => 2017-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 5282 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15718749 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/718749
Method of manufacturing semiconductor device Sep 27, 2017 Issued
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