Search

Bradley Smith

Examiner (ID: 12315, Phone: (571)272-1884 , Office: P/2817 )

Most Active Art Unit
2817
Art Unit(s)
2829, 2894, 2818, 2817, 2824, 2891
Total Applications
1806
Issued Applications
1488
Pending Applications
116
Abandoned Applications
231

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 13006365 [patent_doc_number] => 10026857 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-07-17 [patent_title] => Assembly and mounting of solar cells on airfoils [patent_app_type] => utility [patent_app_number] => 15/359814 [patent_app_country] => US [patent_app_date] => 2016-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 3568 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15359814 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/359814
Assembly and mounting of solar cells on airfoils Nov 22, 2016 Issued
Array ( [id] => 12759976 [patent_doc_number] => 20180145160 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-24 [patent_title] => HETEROJUNCTION BIPOLAR TRANSISTOR DEVICE INTEGRATION SCHEMES ON A SAME WAFER [patent_app_type] => utility [patent_app_number] => 15/360295 [patent_app_country] => US [patent_app_date] => 2016-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3525 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15360295 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/360295
Heterojunction bipolar transistor device integration schemes on a same wafer Nov 22, 2016 Issued
Array ( [id] => 12256907 [patent_doc_number] => 09929056 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-03-27 [patent_title] => 'Method for forming gate structures in different operation voltages' [patent_app_type] => utility [patent_app_number] => 15/359389 [patent_app_country] => US [patent_app_date] => 2016-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 3714 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15359389 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/359389
Method for forming gate structures in different operation voltages Nov 21, 2016 Issued
Array ( [id] => 12047282 [patent_doc_number] => 09824891 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-11-21 [patent_title] => 'Method of manufacturing the thin film' [patent_app_type] => utility [patent_app_number] => 15/358517 [patent_app_country] => US [patent_app_date] => 2016-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2397 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 386 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15358517 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/358517
Method of manufacturing the thin film Nov 21, 2016 Issued
Array ( [id] => 11652769 [patent_doc_number] => 20170148670 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-25 [patent_title] => 'METHODS FOR FORMING LOW-RESISTANCE CONTACTS THROUGH INTEGRATED PROCESS FLOW SYSTEMS' [patent_app_type] => utility [patent_app_number] => 15/358690 [patent_app_country] => US [patent_app_date] => 2016-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4813 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15358690 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/358690
Methods for forming low-resistance contacts through integrated process flow systems Nov 21, 2016 Issued
Array ( [id] => 13243333 [patent_doc_number] => 10134878 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-11-20 [patent_title] => Oxygen vacancy of IGZO passivation by fluorine treatment [patent_app_type] => utility [patent_app_number] => 15/359325 [patent_app_country] => US [patent_app_date] => 2016-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 18 [patent_no_of_words] => 5666 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15359325 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/359325
Oxygen vacancy of IGZO passivation by fluorine treatment Nov 21, 2016 Issued
Array ( [id] => 13019131 [patent_doc_number] => 10032682 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-07-24 [patent_title] => Multi-die wafer-level test and assembly without comprehensive individual die singulation [patent_app_type] => utility [patent_app_number] => 15/359280 [patent_app_country] => US [patent_app_date] => 2016-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 39 [patent_no_of_words] => 8394 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15359280 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/359280
Multi-die wafer-level test and assembly without comprehensive individual die singulation Nov 21, 2016 Issued
Array ( [id] => 12759433 [patent_doc_number] => 20180144979 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-24 [patent_title] => SELF-ALIGNED LITHOGRAPHIC PATTERNING [patent_app_type] => utility [patent_app_number] => 15/359037 [patent_app_country] => US [patent_app_date] => 2016-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3688 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15359037 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/359037
Self-aligned lithographic patterning Nov 21, 2016 Issued
Array ( [id] => 11578634 [patent_doc_number] => 09633904 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-04-25 [patent_title] => 'Method for manufacturing semiconductor device with epitaxial structure' [patent_app_type] => utility [patent_app_number] => 15/352528 [patent_app_country] => US [patent_app_date] => 2016-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 5126 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15352528 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/352528
Method for manufacturing semiconductor device with epitaxial structure Nov 14, 2016 Issued
Array ( [id] => 12691606 [patent_doc_number] => 20180122368 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-03 [patent_title] => MULTIPARTY CONVERSATION ASSISTANCE IN MOBILE DEVICES [patent_app_type] => utility [patent_app_number] => 15/342850 [patent_app_country] => US [patent_app_date] => 2016-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8136 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15342850 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/342850
MULTIPARTY CONVERSATION ASSISTANCE IN MOBILE DEVICES Nov 2, 2016 Abandoned
Array ( [id] => 11861920 [patent_doc_number] => 09741609 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-08-22 [patent_title] => 'Middle of line cobalt interconnection' [patent_app_type] => utility [patent_app_number] => 15/340226 [patent_app_country] => US [patent_app_date] => 2016-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4762 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15340226 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/340226
Middle of line cobalt interconnection Oct 31, 2016 Issued
Array ( [id] => 12202578 [patent_doc_number] => 09905650 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-02-27 [patent_title] => 'Uniaxially strained nanowire structure' [patent_app_type] => utility [patent_app_number] => 15/339620 [patent_app_country] => US [patent_app_date] => 2016-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 6828 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15339620 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/339620
Uniaxially strained nanowire structure Oct 30, 2016 Issued
Array ( [id] => 13557433 [patent_doc_number] => 20180330264 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-15 [patent_title] => SYSTEMS AND METHODS FOR DEGENERACY MITIGATION IN A QUANTUM PROCESSOR [patent_app_type] => utility [patent_app_number] => 15/771606 [patent_app_country] => US [patent_app_date] => 2016-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 32148 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15771606 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/771606
Systems and methods for degeneracy mitigation in a quantum processor Oct 26, 2016 Issued
Array ( [id] => 11424821 [patent_doc_number] => 20170032966 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-02 [patent_title] => 'SEMICONDUCTOR CHIP ARRANGEMENT AND METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 15/289990 [patent_app_country] => US [patent_app_date] => 2016-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 10505 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15289990 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/289990
Semiconductor chip arrangement and method thereof Oct 10, 2016 Issued
Array ( [id] => 11587693 [patent_doc_number] => 20170112104 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-04-27 [patent_title] => 'METHOD AND SYSTEM FOR DETERMINING A PHYSIOLOGICAL CONDITION OF A RUMINANT' [patent_app_type] => utility [patent_app_number] => 15/287289 [patent_app_country] => US [patent_app_date] => 2016-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6080 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15287289 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/287289
Method and system for determining a physiological condition of a ruminant Oct 5, 2016 Issued
Array ( [id] => 13640985 [patent_doc_number] => 09847455 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-12-19 [patent_title] => Vertical topology light emitting device [patent_app_type] => utility [patent_app_number] => 15/278642 [patent_app_country] => US [patent_app_date] => 2016-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 29 [patent_no_of_words] => 6405 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15278642 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/278642
Vertical topology light emitting device Sep 27, 2016 Issued
Array ( [id] => 13653183 [patent_doc_number] => 09852912 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-12-26 [patent_title] => Method of manufacturing semiconductor device for reducing grain size of polysilicon [patent_app_type] => utility [patent_app_number] => 15/270638 [patent_app_country] => US [patent_app_date] => 2016-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 2890 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15270638 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/270638
Method of manufacturing semiconductor device for reducing grain size of polysilicon Sep 19, 2016 Issued
Array ( [id] => 11925550 [patent_doc_number] => 09793138 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-17 [patent_title] => 'Thermal processing method for wafer' [patent_app_type] => utility [patent_app_number] => 15/268006 [patent_app_country] => US [patent_app_date] => 2016-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 4034 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15268006 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/268006
Thermal processing method for wafer Sep 15, 2016 Issued
Array ( [id] => 11517606 [patent_doc_number] => 20170084680 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-23 [patent_title] => 'Methods for Forming High-K Dielectric Materials with Tunable Properties' [patent_app_type] => utility [patent_app_number] => 15/264877 [patent_app_country] => US [patent_app_date] => 2016-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4091 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15264877 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/264877
Methods for Forming High-K Dielectric Materials with Tunable Properties Sep 13, 2016 Abandoned
Array ( [id] => 12019648 [patent_doc_number] => 09812358 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-11-07 [patent_title] => 'FinFET structures and methods of forming the same' [patent_app_type] => utility [patent_app_number] => 15/264718 [patent_app_country] => US [patent_app_date] => 2016-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 47 [patent_figures_cnt] => 47 [patent_no_of_words] => 8424 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15264718 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/264718
FinFET structures and methods of forming the same Sep 13, 2016 Issued
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