Search

Bradley Smith

Examiner (ID: 12315, Phone: (571)272-1884 , Office: P/2817 )

Most Active Art Unit
2817
Art Unit(s)
2829, 2894, 2818, 2817, 2824, 2891
Total Applications
1806
Issued Applications
1488
Pending Applications
116
Abandoned Applications
231

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9667959 [patent_doc_number] => 20140231822 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-21 [patent_title] => 'VERTICAL TOPOLOGY LIGHT-EMITTING DEVICE' [patent_app_type] => utility [patent_app_number] => 14/179488 [patent_app_country] => US [patent_app_date] => 2014-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 6566 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14179488 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/179488
Vertical topology light-emitting device Feb 11, 2014 Issued
Array ( [id] => 9515183 [patent_doc_number] => 20140151675 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-05 [patent_title] => 'SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 14/174494 [patent_app_country] => US [patent_app_date] => 2014-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 20218 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14174494 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/174494
Semiconductor device and manufacturing method thereof Feb 5, 2014 Issued
Array ( [id] => 9503422 [patent_doc_number] => 08741735 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-06-03 [patent_title] => 'Method of forming a semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 14/173552 [patent_app_country] => US [patent_app_date] => 2014-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 20 [patent_no_of_words] => 6644 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14173552 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/173552
Method of forming a semiconductor memory device Feb 4, 2014 Issued
Array ( [id] => 9490047 [patent_doc_number] => 20140140453 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-22 [patent_title] => 'STACKED DIGITAL/RF SYSTEM-ON-CHIP WITH INTEGRAL ISOLATION LAYER' [patent_app_type] => utility [patent_app_number] => 14/164352 [patent_app_country] => US [patent_app_date] => 2014-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2372 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14164352 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/164352
Stacked digital/RF system-on-chip with integral isolation layer Jan 26, 2014 Issued
Array ( [id] => 9488388 [patent_doc_number] => 20140138795 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-22 [patent_title] => 'CAPACITORS AND METHODS WITH PRASEODYMIUM OXIDE INSULATORS' [patent_app_type] => utility [patent_app_number] => 14/165121 [patent_app_country] => US [patent_app_date] => 2014-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4728 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14165121 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/165121
Capacitors and methods with praseodymium oxide insulators Jan 26, 2014 Issued
Array ( [id] => 9463472 [patent_doc_number] => 20140127899 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-08 [patent_title] => 'MICROSTRUCTURE MODIFICATION IN COPPER INTERCONNECT STRUCTURES' [patent_app_type] => utility [patent_app_number] => 14/152127 [patent_app_country] => US [patent_app_date] => 2014-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7344 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14152127 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/152127
Microstructure modification in copper interconnect structures Jan 9, 2014 Issued
Array ( [id] => 9460465 [patent_doc_number] => 20140124891 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-08 [patent_title] => 'FUSE DEVICE' [patent_app_type] => utility [patent_app_number] => 14/151862 [patent_app_country] => US [patent_app_date] => 2014-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 4121 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14151862 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/151862
Fuse device Jan 9, 2014 Issued
Array ( [id] => 9449528 [patent_doc_number] => 20140120698 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-01 [patent_title] => 'WAFER DICING USING HYBRID MULTI-STEP LASER SCRIBING PROCESS WITH PLASMA ETCH' [patent_app_type] => utility [patent_app_number] => 14/148499 [patent_app_country] => US [patent_app_date] => 2014-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10082 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14148499 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/148499
Wafer dicing using hybrid multi-step laser scribing process with plasma etch Jan 5, 2014 Issued
Array ( [id] => 11432353 [patent_doc_number] => 09570680 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-02-14 [patent_title] => 'Method for fabricating electronic devices having semiconductor memory unit' [patent_app_type] => utility [patent_app_number] => 14/145782 [patent_app_country] => US [patent_app_date] => 2013-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 81 [patent_no_of_words] => 20252 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14145782 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/145782
Method for fabricating electronic devices having semiconductor memory unit Dec 30, 2013 Issued
Array ( [id] => 9603138 [patent_doc_number] => 20140199820 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-17 [patent_title] => 'METHODS OF FORMING A PATTERN AND METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE USING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/143255 [patent_app_country] => US [patent_app_date] => 2013-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 7384 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14143255 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/143255
Methods of forming a pattern and methods of manufacturing a semiconductor device using the same Dec 29, 2013 Issued
Array ( [id] => 9656851 [patent_doc_number] => 20140227856 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-14 [patent_title] => 'METHODS OF FABRICATING SEMICONDUCTOR DEVICE HAVING SHALLOW TRENCH ISOLATION (STI)' [patent_app_type] => utility [patent_app_number] => 14/138552 [patent_app_country] => US [patent_app_date] => 2013-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 11105 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14138552 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/138552
Methods of fabricating semiconductor device having shallow trench isolation (STI) Dec 22, 2013 Issued
Array ( [id] => 9839104 [patent_doc_number] => 20150031185 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-29 [patent_title] => 'METHODS OF FABRICATING SEMICONDUCTOR DEVICES AND SEMICONDUCTOR DEVICES FABRICATED THEREBY' [patent_app_type] => utility [patent_app_number] => 14/139502 [patent_app_country] => US [patent_app_date] => 2013-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 44 [patent_no_of_words] => 10091 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14139502 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/139502
Methods of fabricating semiconductor devices and semiconductor devices fabricated thereby Dec 22, 2013 Issued
Array ( [id] => 10464046 [patent_doc_number] => 20150349061 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-03 [patent_title] => 'METHODS FOR FABRICATING GRAPHENE DEVICE TOPOGRAPHY AND DEVICES FORMED THEREFROM' [patent_app_type] => utility [patent_app_number] => 14/654776 [patent_app_country] => US [patent_app_date] => 2013-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 22199 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14654776 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/654776
METHODS FOR FABRICATING GRAPHENE DEVICE TOPOGRAPHY AND DEVICES FORMED THEREFROM Dec 20, 2013 Abandoned
Array ( [id] => 9613554 [patent_doc_number] => 20140203411 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-24 [patent_title] => 'PRODUCTION METHOD OF SEMICONDUCTOR DEVICE, SEMICONDUCTOR WAFER, AND SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/134325 [patent_app_country] => US [patent_app_date] => 2013-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5017 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14134325 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/134325
Production method of semiconductor device, semiconductor wafer, and semiconductor device Dec 18, 2013 Issued
Array ( [id] => 9569307 [patent_doc_number] => 20140187020 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-03 [patent_title] => 'METHOD FOR LOW TEMPERATURE LAYER TRANSFER IN THE PREPARATION OF MULTILAYER SEMICONDUTOR DEVICES' [patent_app_type] => utility [patent_app_number] => 14/133893 [patent_app_country] => US [patent_app_date] => 2013-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4447 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14133893 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/133893
Method for low temperature layer transfer in the preparation of multilayer semiconductor devices Dec 18, 2013 Issued
Array ( [id] => 11890909 [patent_doc_number] => 09761474 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-09-12 [patent_title] => 'Methods for processing semiconductor devices' [patent_app_type] => utility [patent_app_number] => 14/134199 [patent_app_country] => US [patent_app_date] => 2013-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 17 [patent_no_of_words] => 6152 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14134199 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/134199
Methods for processing semiconductor devices Dec 18, 2013 Issued
Array ( [id] => 10285968 [patent_doc_number] => 20150170967 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-06-18 [patent_title] => 'Methods for Substrate and Device Fabrications' [patent_app_type] => utility [patent_app_number] => 14/104601 [patent_app_country] => US [patent_app_date] => 2013-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6998 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14104601 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/104601
Methods for Substrate and Device Fabrications Dec 11, 2013 Abandoned
Array ( [id] => 10066878 [patent_doc_number] => 09105740 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-08-11 [patent_title] => 'SONOS type stacks for nonvolatile changetrap memory devices and methods to form the same' [patent_app_type] => utility [patent_app_number] => 14/105041 [patent_app_country] => US [patent_app_date] => 2013-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 44 [patent_no_of_words] => 17074 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14105041 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/105041
SONOS type stacks for nonvolatile changetrap memory devices and methods to form the same Dec 11, 2013 Issued
Array ( [id] => 10617619 [patent_doc_number] => 09337068 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-05-10 [patent_title] => 'Oxygen-containing ceramic hard masks and associated wet-cleans' [patent_app_type] => utility [patent_app_number] => 14/105026 [patent_app_country] => US [patent_app_date] => 2013-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 24 [patent_no_of_words] => 8820 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14105026 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/105026
Oxygen-containing ceramic hard masks and associated wet-cleans Dec 11, 2013 Issued
Array ( [id] => 9546186 [patent_doc_number] => 20140170834 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-19 [patent_title] => 'METHOD FOR MANUFACTURING A HYBRID SOI/BULK SEMICONDUCTOR WAFER' [patent_app_type] => utility [patent_app_number] => 14/104903 [patent_app_country] => US [patent_app_date] => 2013-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3279 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14104903 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/104903
Method for manufacturing a hybrid SOI/bulk semiconductor wafer Dec 11, 2013 Issued
Menu