Search

Bradley Smith

Examiner (ID: 12315, Phone: (571)272-1884 , Office: P/2817 )

Most Active Art Unit
2817
Art Unit(s)
2829, 2894, 2818, 2817, 2824, 2891
Total Applications
1806
Issued Applications
1488
Pending Applications
116
Abandoned Applications
231

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8896643 [patent_doc_number] => 08476164 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-07-02 [patent_title] => 'Method of manufacturing semiconductor device with silicide' [patent_app_type] => utility [patent_app_number] => 13/661111 [patent_app_country] => US [patent_app_date] => 2012-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2613 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13661111 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/661111
Method of manufacturing semiconductor device with silicide Oct 25, 2012 Issued
Array ( [id] => 9446334 [patent_doc_number] => 20140117502 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-01 [patent_title] => 'METHOD FOR PROCESSING A SEMICONDUCTOR CARRIER, A SEMICONDUCTOR CHIP ARRANGEMENT AND A METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/659956 [patent_app_country] => US [patent_app_date] => 2012-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 10427 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13659956 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/659956
Method for processing a semiconductor carrier, a semiconductor chip arrangement and a method for manufacturing a semiconductor device Oct 24, 2012 Issued
Array ( [id] => 9844180 [patent_doc_number] => 08946095 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-02-03 [patent_title] => 'Method of forming interlayer dielectric film above metal gate of semiconductor device' [patent_app_type] => utility [patent_app_number] => 13/660363 [patent_app_country] => US [patent_app_date] => 2012-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4027 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13660363 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/660363
Method of forming interlayer dielectric film above metal gate of semiconductor device Oct 24, 2012 Issued
Array ( [id] => 8968558 [patent_doc_number] => 08507369 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-13 [patent_title] => 'Method for producing silicon nanowire devices' [patent_app_type] => utility [patent_app_number] => 13/659907 [patent_app_country] => US [patent_app_date] => 2012-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 2348 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13659907 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/659907
Method for producing silicon nanowire devices Oct 23, 2012 Issued
Array ( [id] => 9951068 [patent_doc_number] => 08999854 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-04-07 [patent_title] => 'Method for manufacturing silicon carbide semiconductor device' [patent_app_type] => utility [patent_app_number] => 13/658583 [patent_app_country] => US [patent_app_date] => 2012-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 23 [patent_no_of_words] => 7739 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13658583 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/658583
Method for manufacturing silicon carbide semiconductor device Oct 22, 2012 Issued
Array ( [id] => 8792195 [patent_doc_number] => 20130109164 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-02 [patent_title] => 'REMOTE PLASMA RADICAL TREATMENT OF SILICON OXIDE' [patent_app_type] => utility [patent_app_number] => 13/658594 [patent_app_country] => US [patent_app_date] => 2012-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8500 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13658594 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/658594
Remote plasma radical treatment of silicon oxide Oct 22, 2012 Issued
Array ( [id] => 8780158 [patent_doc_number] => 20130102133 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-04-25 [patent_title] => 'METHOD AND APPARATUS FOR FABRICATING SILICON HETEROJUNCTION SOLAR CELLS' [patent_app_type] => utility [patent_app_number] => 13/656420 [patent_app_country] => US [patent_app_date] => 2012-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 11405 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13656420 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/656420
Method and apparatus for fabricating silicon heterojunction solar cells Oct 18, 2012 Issued
Array ( [id] => 9413534 [patent_doc_number] => 08697571 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-04-15 [patent_title] => 'Power MOSFET contact metallization' [patent_app_type] => utility [patent_app_number] => 13/654230 [patent_app_country] => US [patent_app_date] => 2012-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 2318 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13654230 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/654230
Power MOSFET contact metallization Oct 16, 2012 Issued
Array ( [id] => 9094413 [patent_doc_number] => 20130273724 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-17 [patent_title] => 'METHOD FOR CRYSTALLIZING AMORPHOUS SILICON THIN FILM AND METHOD FOR FABRICATING POLY CRYSTALLINE THIN FILM TRANSISTOR USING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/630148 [patent_app_country] => US [patent_app_date] => 2012-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 15891 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13630148 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/630148
Method for crystallizing amorphous silicon thin film and method for fabricating poly crystalline thin film transistor using the same Oct 15, 2012 Issued
Array ( [id] => 9875198 [patent_doc_number] => 08962465 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-02-24 [patent_title] => 'Methods of forming gated devices' [patent_app_type] => utility [patent_app_number] => 13/652305 [patent_app_country] => US [patent_app_date] => 2012-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 19 [patent_no_of_words] => 4911 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13652305 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/652305
Methods of forming gated devices Oct 14, 2012 Issued
Array ( [id] => 12554109 [patent_doc_number] => 10014261 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-03 [patent_title] => Microchip charge patterning [patent_app_type] => utility [patent_app_number] => 13/652194 [patent_app_country] => US [patent_app_date] => 2012-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 16 [patent_no_of_words] => 2470 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13652194 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/652194
Microchip charge patterning Oct 14, 2012 Issued
Array ( [id] => 8888611 [patent_doc_number] => 20130161795 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-27 [patent_title] => 'MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE, PROCESSING METHOD OF SEMICONDUCTOR WAFER, SEMICONDUCTOR WAFER' [patent_app_type] => utility [patent_app_number] => 13/650465 [patent_app_country] => US [patent_app_date] => 2012-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 34 [patent_no_of_words] => 9393 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13650465 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/650465
Manufacturing method of semiconductor device, processing method of semiconductor wafer, semiconductor wafer Oct 11, 2012 Issued
Array ( [id] => 12168383 [patent_doc_number] => 09887155 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-02-06 [patent_title] => 'Multiple metal layer semiconductor device and low temperature stacking method of fabricating the same' [patent_app_type] => utility [patent_app_number] => 13/651045 [patent_app_country] => US [patent_app_date] => 2012-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4755 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 317 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13651045 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/651045
Multiple metal layer semiconductor device and low temperature stacking method of fabricating the same Oct 11, 2012 Issued
Array ( [id] => 9232728 [patent_doc_number] => 08598033 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-12-03 [patent_title] => 'Method for forming a salicide layer' [patent_app_type] => utility [patent_app_number] => 13/646726 [patent_app_country] => US [patent_app_date] => 2012-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3325 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13646726 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/646726
Method for forming a salicide layer Oct 6, 2012 Issued
Array ( [id] => 8943999 [patent_doc_number] => 08497177 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-07-30 [patent_title] => 'Method of making a FinFET device' [patent_app_type] => utility [patent_app_number] => 13/645305 [patent_app_country] => US [patent_app_date] => 2012-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3550 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13645305 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/645305
Method of making a FinFET device Oct 3, 2012 Issued
Array ( [id] => 10309337 [patent_doc_number] => 20150194338 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-09 [patent_title] => 'Method For Preparing Ultra-thin Material On Insulator Through Adsorption By Doped Ultra-thin Layer' [patent_app_type] => utility [patent_app_number] => 13/825079 [patent_app_country] => US [patent_app_date] => 2012-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3913 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13825079 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/825079
Method for preparing ultra-thin material on insulator through adsorption by doped ultra-thin layer Sep 24, 2012 Issued
Array ( [id] => 9205507 [patent_doc_number] => 20140004684 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-02 [patent_title] => 'Method for Preparing GOI Chip Structure' [patent_app_type] => utility [patent_app_number] => 13/825010 [patent_app_country] => US [patent_app_date] => 2012-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4218 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13825010 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/825010
Method for preparing GOI chip structure Sep 24, 2012 Issued
Array ( [id] => 8603964 [patent_doc_number] => 20130009276 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-10 [patent_title] => 'METHODS OF FILLING ISOLATION TRENCHES FOR SEMICONDUCTOR DEVICES AND RESULTING STRUCTURES' [patent_app_type] => utility [patent_app_number] => 13/616199 [patent_app_country] => US [patent_app_date] => 2012-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3358 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13616199 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/616199
METHODS OF FILLING ISOLATION TRENCHES FOR SEMICONDUCTOR DEVICES AND RESULTING STRUCTURES Sep 13, 2012 Abandoned
Array ( [id] => 8519665 [patent_doc_number] => 20120319073 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-20 [patent_title] => 'VARIABLE RESISTANCE MEMORY DEVICE HAVING REDUCED BOTTOM CONTACT AREA AND METHOD OF FORMING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/591891 [patent_app_country] => US [patent_app_date] => 2012-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 3878 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13591891 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/591891
Variable resistance memory device having reduced bottom contact area and method of forming the same Aug 21, 2012 Issued
Array ( [id] => 10870203 [patent_doc_number] => 08895399 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-11-25 [patent_title] => 'Integrated circuit and method of forming sealed trench junction termination' [patent_app_type] => utility [patent_app_number] => 13/568410 [patent_app_country] => US [patent_app_date] => 2012-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 20 [patent_no_of_words] => 9910 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13568410 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/568410
Integrated circuit and method of forming sealed trench junction termination Aug 6, 2012 Issued
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