Search

Bradley Smith

Examiner (ID: 12315, Phone: (571)272-1884 , Office: P/2817 )

Most Active Art Unit
2817
Art Unit(s)
2829, 2894, 2818, 2817, 2824, 2891
Total Applications
1806
Issued Applications
1488
Pending Applications
116
Abandoned Applications
231

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9250345 [patent_doc_number] => 08614123 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-12-24 [patent_title] => 'Method of forming a semiconductor device by using sacrificial gate electrodes and sacrificial self-aligned contact structures' [patent_app_type] => utility [patent_app_number] => 13/305131 [patent_app_country] => US [patent_app_date] => 2011-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 5919 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13305131 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/305131
Method of forming a semiconductor device by using sacrificial gate electrodes and sacrificial self-aligned contact structures Nov 27, 2011 Issued
Array ( [id] => 8359128 [patent_doc_number] => 20120214295 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-23 [patent_title] => 'METHOD FOR MANUFACTURING TRANSISTOR' [patent_app_type] => utility [patent_app_number] => 13/305726 [patent_app_country] => US [patent_app_date] => 2011-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3044 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13305726 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/305726
Method for manufacturing transistor Nov 27, 2011 Issued
Array ( [id] => 9440820 [patent_doc_number] => 08709930 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-04-29 [patent_title] => 'Semiconductor process' [patent_app_type] => utility [patent_app_number] => 13/304416 [patent_app_country] => US [patent_app_date] => 2011-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 19 [patent_no_of_words] => 4870 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13304416 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/304416
Semiconductor process Nov 24, 2011 Issued
Array ( [id] => 8227979 [patent_doc_number] => 20120142177 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-07 [patent_title] => 'METHODS OF MANUFACTURING A WIRING STRUCTURE AND METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/299538 [patent_app_country] => US [patent_app_date] => 2011-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 15400 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13299538 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/299538
METHODS OF MANUFACTURING A WIRING STRUCTURE AND METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE Nov 17, 2011 Abandoned
Array ( [id] => 9710710 [patent_doc_number] => 08835278 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-09-16 [patent_title] => 'Method for forming a buried dielectric layer underneath a semiconductor fin' [patent_app_type] => utility [patent_app_number] => 13/885884 [patent_app_country] => US [patent_app_date] => 2011-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 25 [patent_no_of_words] => 7982 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13885884 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/885884
Method for forming a buried dielectric layer underneath a semiconductor fin Nov 15, 2011 Issued
Array ( [id] => 8802237 [patent_doc_number] => 08440511 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-05-14 [patent_title] => 'Method for manufacturing multi-gate transistor device' [patent_app_type] => utility [patent_app_number] => 13/298264 [patent_app_country] => US [patent_app_date] => 2011-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2924 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13298264 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/298264
Method for manufacturing multi-gate transistor device Nov 15, 2011 Issued
Array ( [id] => 8659613 [patent_doc_number] => 20130040442 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-02-14 [patent_title] => 'METHOD OF MANUFACTURING GaN-BASED FILM' [patent_app_type] => utility [patent_app_number] => 13/643206 [patent_app_country] => US [patent_app_date] => 2011-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 15945 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13643206 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/643206
Method of manufacturing GaN-based film Nov 9, 2011 Issued
Array ( [id] => 9203798 [patent_doc_number] => 20140002976 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-02 [patent_title] => 'RECESSED BOTTOM-ELECTRODE CAPACITORS AND METHODS OF ASSEMBLING SAME' [patent_app_type] => utility [patent_app_number] => 13/997974 [patent_app_country] => US [patent_app_date] => 2011-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6350 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13997974 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/997974
RECESSED BOTTOM-ELECTRODE CAPACITORS AND METHODS OF ASSEMBLING SAME Nov 9, 2011 Abandoned
Array ( [id] => 8659613 [patent_doc_number] => 20130040442 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-02-14 [patent_title] => 'METHOD OF MANUFACTURING GaN-BASED FILM' [patent_app_type] => utility [patent_app_number] => 13/643206 [patent_app_country] => US [patent_app_date] => 2011-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 15945 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13643206 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/643206
Method of manufacturing GaN-based film Nov 9, 2011 Issued
Array ( [id] => 8659613 [patent_doc_number] => 20130040442 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-02-14 [patent_title] => 'METHOD OF MANUFACTURING GaN-BASED FILM' [patent_app_type] => utility [patent_app_number] => 13/643206 [patent_app_country] => US [patent_app_date] => 2011-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 15945 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13643206 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/643206
Method of manufacturing GaN-based film Nov 9, 2011 Issued
Array ( [id] => 8659613 [patent_doc_number] => 20130040442 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-02-14 [patent_title] => 'METHOD OF MANUFACTURING GaN-BASED FILM' [patent_app_type] => utility [patent_app_number] => 13/643206 [patent_app_country] => US [patent_app_date] => 2011-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 15945 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13643206 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/643206
Method of manufacturing GaN-based film Nov 9, 2011 Issued
Array ( [id] => 7772969 [patent_doc_number] => 20120037903 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-02-16 [patent_title] => 'Method For Manufacturing Semiconductor Device, Semiconductor Device And Electronic Appliance' [patent_app_type] => utility [patent_app_number] => 13/282557 [patent_app_country] => US [patent_app_date] => 2011-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 28657 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0037/20120037903.pdf [firstpage_image] =>[orig_patent_app_number] => 13282557 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/282557
Method for manufacturing semiconductor device, semiconductor device and electronic appliance Oct 26, 2011 Issued
Array ( [id] => 9923410 [patent_doc_number] => 08981379 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-17 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 13/239853 [patent_app_country] => US [patent_app_date] => 2011-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 74 [patent_no_of_words] => 26176 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13239853 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/239853
Semiconductor device Sep 21, 2011 Issued
Array ( [id] => 8055177 [patent_doc_number] => 20120077327 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-29 [patent_title] => 'Formation of a Shallow Trench Isolation Structure' [patent_app_type] => utility [patent_app_number] => 13/236815 [patent_app_country] => US [patent_app_date] => 2011-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5983 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0077/20120077327.pdf [firstpage_image] =>[orig_patent_app_number] => 13236815 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/236815
Formation of a Shallow Trench Isolation Structure Sep 19, 2011 Abandoned
Array ( [id] => 10837895 [patent_doc_number] => 08865567 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-10-21 [patent_title] => 'Method of manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 13/817112 [patent_app_country] => US [patent_app_date] => 2011-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 7881 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13817112 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/817112
Method of manufacturing semiconductor device Sep 19, 2011 Issued
Array ( [id] => 9046761 [patent_doc_number] => 08541315 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-09-24 [patent_title] => 'High throughput epitaxial lift off for flexible electronics' [patent_app_type] => utility [patent_app_number] => 13/236119 [patent_app_country] => US [patent_app_date] => 2011-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 14 [patent_no_of_words] => 6130 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13236119 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/236119
High throughput epitaxial lift off for flexible electronics Sep 18, 2011 Issued
Array ( [id] => 8720778 [patent_doc_number] => 20130071995 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-03-21 [patent_title] => 'Method of Manufacturing a Semiconductor Device' [patent_app_type] => utility [patent_app_number] => 13/234296 [patent_app_country] => US [patent_app_date] => 2011-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5056 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13234296 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/234296
Method of manufacturing a semiconductor device Sep 15, 2011 Issued
Array ( [id] => 10502531 [patent_doc_number] => 09230933 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-01-05 [patent_title] => 'Semiconductor device and method of forming conductive protrusion over conductive pillars or bond pads as fixed offset vertical interconnect structure' [patent_app_type] => utility [patent_app_number] => 13/234366 [patent_app_country] => US [patent_app_date] => 2011-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 50 [patent_no_of_words] => 9541 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13234366 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/234366
Semiconductor device and method of forming conductive protrusion over conductive pillars or bond pads as fixed offset vertical interconnect structure Sep 15, 2011 Issued
Array ( [id] => 8720802 [patent_doc_number] => 20130072019 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-03-21 [patent_title] => 'METHODS FOR FORMING SEMICONDUCTOR DEVICES' [patent_app_type] => utility [patent_app_number] => 13/235194 [patent_app_country] => US [patent_app_date] => 2011-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2836 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13235194 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/235194
Methods for forming semiconductor devices Sep 15, 2011 Issued
Array ( [id] => 8720795 [patent_doc_number] => 20130072012 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-03-21 [patent_title] => 'Method For Forming Package Substrate With Ultra-Thin Seed Layer' [patent_app_type] => utility [patent_app_number] => 13/235347 [patent_app_country] => US [patent_app_date] => 2011-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2977 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13235347 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/235347
Method For Forming Package Substrate With Ultra-Thin Seed Layer Sep 15, 2011 Abandoned
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