
Brandon Bowers
Examiner (ID: 10602, Phone: (571)272-1888 , Office: P/2851 )
| Most Active Art Unit | 2851 |
| Art Unit(s) | 2825, 2851 |
| Total Applications | 889 |
| Issued Applications | 747 |
| Pending Applications | 56 |
| Abandoned Applications | 107 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 19702866
[patent_doc_number] => 12196887
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2025-01-14
[patent_title] => Silicon photonic chip, LiDAR, and mobile device
[patent_app_type] => utility
[patent_app_number] => 18/764122
[patent_app_country] => US
[patent_app_date] => 2024-07-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 8395
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 229
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18764122
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/764122 | Silicon photonic chip, LiDAR, and mobile device | Jul 2, 2024 | Issued |
Array
(
[id] => 19484238
[patent_doc_number] => 20240332280
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-10-03
[patent_title] => INTEGRATED CIRCUIT AND METHOD OF FORMING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/739703
[patent_app_country] => US
[patent_app_date] => 2024-06-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 19187
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 146
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18739703
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/739703 | INTEGRATED CIRCUIT AND METHOD OF FORMING THE SAME | Jun 10, 2024 | Pending |
Array
(
[id] => 19484238
[patent_doc_number] => 20240332280
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-10-03
[patent_title] => INTEGRATED CIRCUIT AND METHOD OF FORMING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/739703
[patent_app_country] => US
[patent_app_date] => 2024-06-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 19187
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 146
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18739703
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/739703 | INTEGRATED CIRCUIT AND METHOD OF FORMING THE SAME | Jun 10, 2024 | Pending |
Array
(
[id] => 19451414
[patent_doc_number] => 20240311544
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-09-19
[patent_title] => SEMICONDUCTOR DEVICE INCLUDING STANDARD CELL HAVING SPLIT PORTIONS
[patent_app_type] => utility
[patent_app_number] => 18/676537
[patent_app_country] => US
[patent_app_date] => 2024-05-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13300
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 78
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18676537
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/676537 | SEMICONDUCTOR DEVICE INCLUDING STANDARD CELL HAVING SPLIT PORTIONS | May 28, 2024 | Pending |
Array
(
[id] => 19810795
[patent_doc_number] => 12242183
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-03-04
[patent_title] => Enforcing mask synthesis consistency across random areas of integrated circuit chips
[patent_app_type] => utility
[patent_app_number] => 18/626291
[patent_app_country] => US
[patent_app_date] => 2024-04-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 31
[patent_no_of_words] => 12057
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 161
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18626291
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/626291 | Enforcing mask synthesis consistency across random areas of integrated circuit chips | Apr 2, 2024 | Issued |
Array
(
[id] => 19303913
[patent_doc_number] => 20240232493
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-07-11
[patent_title] => NOISE SIMULATION SYSTEM
[patent_app_type] => utility
[patent_app_number] => 18/610245
[patent_app_country] => US
[patent_app_date] => 2024-03-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3688
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -7
[patent_words_short_claim] => 128
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18610245
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/610245 | Noise simulation system | Mar 18, 2024 | Issued |
Array
(
[id] => 19413733
[patent_doc_number] => 12079553
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2024-09-03
[patent_title] => Method, medium and system for determining demolition points of large building
[patent_app_type] => utility
[patent_app_number] => 18/433337
[patent_app_country] => US
[patent_app_date] => 2024-02-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 6888
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 560
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18433337
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/433337 | Method, medium and system for determining demolition points of large building | Feb 4, 2024 | Issued |
Array
(
[id] => 19174846
[patent_doc_number] => 20240160820
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-05-16
[patent_title] => Attribute-Point-Based Timing Constraint Formal Verification
[patent_app_type] => utility
[patent_app_number] => 18/418546
[patent_app_country] => US
[patent_app_date] => 2024-01-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5654
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 37
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18418546
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/418546 | Attribute-Point-Based Timing Constraint Formal Verification | Jan 21, 2024 | Pending |
Array
(
[id] => 19174846
[patent_doc_number] => 20240160820
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-05-16
[patent_title] => Attribute-Point-Based Timing Constraint Formal Verification
[patent_app_type] => utility
[patent_app_number] => 18/418546
[patent_app_country] => US
[patent_app_date] => 2024-01-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5654
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 37
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18418546
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/418546 | Attribute-Point-Based Timing Constraint Formal Verification | Jan 21, 2024 | Pending |
Array
(
[id] => 19303912
[patent_doc_number] => 20240232492
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-07-11
[patent_title] => Field Programmable Analog Array
[patent_app_type] => utility
[patent_app_number] => 18/538389
[patent_app_country] => US
[patent_app_date] => 2023-12-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12615
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18538389
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/538389 | Field programmable analog array | Dec 12, 2023 | Issued |
Array
(
[id] => 19053470
[patent_doc_number] => 20240095439
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-03-21
[patent_title] => DEVICES WITH TRACK-BASED FILL (TBF) METAL PATTERNING
[patent_app_type] => utility
[patent_app_number] => 18/526324
[patent_app_country] => US
[patent_app_date] => 2023-12-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9233
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 75
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18526324
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/526324 | DEVICES WITH TRACK-BASED FILL (TBF) METAL PATTERNING | Nov 30, 2023 | Pending |
Array
(
[id] => 18990019
[patent_doc_number] => 20240061988
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-02-22
[patent_title] => INTEGRATED ROUTING ASSEMBLY AND SYSTEM USING SAME
[patent_app_type] => utility
[patent_app_number] => 18/385406
[patent_app_country] => US
[patent_app_date] => 2023-10-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6585
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -7
[patent_words_short_claim] => 143
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18385406
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/385406 | INTEGRATED ROUTING ASSEMBLY AND SYSTEM USING SAME | Oct 30, 2023 | Pending |
Array
(
[id] => 19443352
[patent_doc_number] => 12093620
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2024-09-17
[patent_title] => Multi-cycle power analysis of integrated circuit designs
[patent_app_type] => utility
[patent_app_number] => 18/385285
[patent_app_country] => US
[patent_app_date] => 2023-10-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 20852
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 154
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18385285
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/385285 | Multi-cycle power analysis of integrated circuit designs | Oct 29, 2023 | Issued |
Array
(
[id] => 18957696
[patent_doc_number] => 20240046023
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-02-08
[patent_title] => METHODS AND SYSTEMS FOR GENERATING SHAPE DATA FOR ELECTRONIC DESIGNS
[patent_app_type] => utility
[patent_app_number] => 18/488823
[patent_app_country] => US
[patent_app_date] => 2023-10-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5388
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 120
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18488823
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/488823 | Methods and systems for generating shape data for electronic designs | Oct 16, 2023 | Issued |
Array
(
[id] => 19942513
[patent_doc_number] => 12314645
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-05-27
[patent_title] => Method and system for verifying a sorter
[patent_app_type] => utility
[patent_app_number] => 18/377746
[patent_app_country] => US
[patent_app_date] => 2023-10-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 12
[patent_no_of_words] => 6954
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 97
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18377746
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/377746 | Method and system for verifying a sorter | Oct 5, 2023 | Issued |
Array
(
[id] => 18889917
[patent_doc_number] => 11868690
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2024-01-09
[patent_title] => Method, device, electronic equipment and medium for analyzing disaster prevention and mitigation effectiveness of ecological seawall
[patent_app_type] => utility
[patent_app_number] => 18/458829
[patent_app_country] => US
[patent_app_date] => 2023-08-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 10331
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 303
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18458829
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/458829 | Method, device, electronic equipment and medium for analyzing disaster prevention and mitigation effectiveness of ecological seawall | Aug 29, 2023 | Issued |
Array
(
[id] => 18773119
[patent_doc_number] => 20230367948
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-11-16
[patent_title] => SEMICONDUCTOR DEVICE INCLUDING STANDARD CELL HAVING SPLIT PORTIONS
[patent_app_type] => utility
[patent_app_number] => 18/360799
[patent_app_country] => US
[patent_app_date] => 2023-07-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13657
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 135
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18360799
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/360799 | Semiconductor device including standard cell having split portions | Jul 26, 2023 | Issued |
Array
(
[id] => 18773119
[patent_doc_number] => 20230367948
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-11-16
[patent_title] => SEMICONDUCTOR DEVICE INCLUDING STANDARD CELL HAVING SPLIT PORTIONS
[patent_app_type] => utility
[patent_app_number] => 18/360799
[patent_app_country] => US
[patent_app_date] => 2023-07-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13657
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 135
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18360799
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/360799 | Semiconductor device including standard cell having split portions | Jul 26, 2023 | Issued |
Array
(
[id] => 19885950
[patent_doc_number] => 12271667
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-04-08
[patent_title] => System on chip (SOC) current profile model for integrated voltage regulator (IVR) co-design
[patent_app_type] => utility
[patent_app_number] => 18/329109
[patent_app_country] => US
[patent_app_date] => 2023-06-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 5614
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 227
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18329109
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/329109 | System on chip (SOC) current profile model for integrated voltage regulator (IVR) co-design | Jun 4, 2023 | Issued |
Array
(
[id] => 19363143
[patent_doc_number] => 20240265177
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-08-08
[patent_title] => MULTI-SCALE METHOD FOR HIGH-TEMPERATURE STRUCTURE ABLATION PREDICTION OF HYPERSONIC VEHICLES
[patent_app_type] => utility
[patent_app_number] => 18/203713
[patent_app_country] => US
[patent_app_date] => 2023-05-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5247
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -6
[patent_words_short_claim] => 413
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18203713
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/203713 | Multi-scale method for high-temperature structure ablation prediction of hypersonic vehicles | May 30, 2023 | Issued |