Brandon Bowers

Array ( [id] => 16424116 [patent_doc_number] => 20200349314 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-05 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/933281 [patent_app_country] => US [patent_app_date] => 2020-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10877 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16933281 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17666691 [patent_doc_number] => 11360382 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-06-14 [patent_title] => Enforcing mask synthesis consistency across random areas of integrated circuit chips [patent_app_type] => utility [patent_app_number] => 16/929700 [patent_app_country] => US [patent_app_date] => 2020-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 31 [patent_no_of_words] => 12016 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16929700 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16919023 [patent_doc_number] => 20210192115 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-24 [patent_title] => MECHANISM TO PLACE REPEATERS ON EXISTING STRUCTURED ROUTING BASED ON GEOMETRIC CONSIDERATION AND TO PLACE LATTICE MULTI-LAYER METAL STRUCTURES OVER CELLS [patent_app_type] => utility [patent_app_number] => 16/928975 [patent_app_country] => US [patent_app_date] => 2020-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15159 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16928975 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16880224 [patent_doc_number] => 11030374 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-06-08 [patent_title] => Filling vacant areas of an integrated circuit design [patent_app_type] => utility [patent_app_number] => 16/909997 [patent_app_country] => US [patent_app_date] => 2020-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 9214 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16909997 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17623845 [patent_doc_number] => 11342914 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-24 [patent_title] => Integrated circuit having state machine-driven flops in wrapper chains for device testing [patent_app_type] => utility [patent_app_number] => 16/906877 [patent_app_country] => US [patent_app_date] => 2020-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 15781 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16906877 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17423380 [patent_doc_number] => 11256838 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-22 [patent_title] => Establishing method for timing model [patent_app_type] => utility [patent_app_number] => 16/865406 [patent_app_country] => US [patent_app_date] => 2020-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 4362 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16865406 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16439390 [patent_doc_number] => 20200356716 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-12 [patent_title] => IC DESIGN DATA BASE GENERATING METHOD, IC DESIGN METHOD, AND ELECTRONIC DEVICE USING THE METHODS [patent_app_type] => utility [patent_app_number] => 16/862575 [patent_app_country] => US [patent_app_date] => 2020-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3864 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16862575 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16644599 [patent_doc_number] => 10922456 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-02-16 [patent_title] => Circuit modification for efficient electro-static discharge analysis of integrated circuits [patent_app_type] => utility [patent_app_number] => 16/864080 [patent_app_country] => US [patent_app_date] => 2020-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6949 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16864080 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17395082 [patent_doc_number] => 11244096 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-08 [patent_title] => Simulating operation of an electronic device tracing using port mirroring [patent_app_type] => utility [patent_app_number] => 16/861255 [patent_app_country] => US [patent_app_date] => 2020-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4579 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16861255 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16488179 [patent_doc_number] => 20200381788 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-03 [patent_title] => HEATING METHOD FOR RECHARGEABLE BATTERY, CONTROL UNIT AND HEATING CIRCUIT [patent_app_type] => utility [patent_app_number] => 16/860408 [patent_app_country] => US [patent_app_date] => 2020-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8022 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16860408 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16676041 [patent_doc_number] => 20210064807 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-04 [patent_title] => METHODS OF DESIGNING LAYOUTS OF SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 16/859323 [patent_app_country] => US [patent_app_date] => 2020-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8487 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16859323 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17809690 [patent_doc_number] => 20220261525 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-18 [patent_title] => SYSTEM-IN-PACKAGE TECHNOLOGY-BASED PROCESS DESIGN METHOD AND SYSTEM, MEDIUM, AND DEVICE [patent_app_type] => utility [patent_app_number] => 17/611546 [patent_app_country] => US [patent_app_date] => 2020-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6746 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17611546 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17809690 [patent_doc_number] => 20220261525 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-18 [patent_title] => SYSTEM-IN-PACKAGE TECHNOLOGY-BASED PROCESS DESIGN METHOD AND SYSTEM, MEDIUM, AND DEVICE [patent_app_type] => utility [patent_app_number] => 17/611546 [patent_app_country] => US [patent_app_date] => 2020-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6746 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17611546 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17031075 [patent_doc_number] => 11092885 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-17 [patent_title] => Manufacturing methods of semiconductor devices [patent_app_type] => utility [patent_app_number] => 16/845459 [patent_app_country] => US [patent_app_date] => 2020-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 6271 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16845459 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18546412 [patent_doc_number] => 11719760 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-08 [patent_title] => Probabilistic determination of transformer end of life [patent_app_type] => utility [patent_app_number] => 16/843684 [patent_app_country] => US [patent_app_date] => 2020-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 27 [patent_no_of_words] => 9415 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16843684 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16535550 [patent_doc_number] => 10878151 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-12-29 [patent_title] => Glitch occurring point detection apparatus and method [patent_app_type] => utility [patent_app_number] => 16/843720 [patent_app_country] => US [patent_app_date] => 2020-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3673 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16843720 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16363494 [patent_doc_number] => 20200320245 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-08 [patent_title] => Test Generation Systems And Methods [patent_app_type] => utility [patent_app_number] => 16/841346 [patent_app_country] => US [patent_app_date] => 2020-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7146 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16841346 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16864894 [patent_doc_number] => 11023638 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-01 [patent_title] => Method for reducing cost and increasing accuracy of variational quantum circuit optimization [patent_app_type] => utility [patent_app_number] => 16/840935 [patent_app_country] => US [patent_app_date] => 2020-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 6297 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16840935 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17751169 [patent_doc_number] => 20220229374 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-21 [patent_title] => METHOD OF DETERMINING CHARACTERISTIC OF PATTERNING PROCESS BASED ON DEFECT FOR REDUCING HOTSPOT [patent_app_type] => utility [patent_app_number] => 17/605358 [patent_app_country] => US [patent_app_date] => 2020-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 25370 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17605358 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16834263 [patent_doc_number] => 11010518 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-18 [patent_title] => Mapping logical qubits on a quantum circuit [patent_app_type] => utility [patent_app_number] => 16/819994 [patent_app_country] => US [patent_app_date] => 2020-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 14330 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16819994 [rel_patent_id] =>[rel_patent_doc_number] =>)