
Brandon Bowers
Examiner (ID: 15542, Phone: (571)272-1888 , Office: P/2851 )
| Most Active Art Unit | 2851 |
| Art Unit(s) | 2825, 2851 |
| Total Applications | 903 |
| Issued Applications | 756 |
| Pending Applications | 52 |
| Abandoned Applications | 108 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 16552083
[patent_doc_number] => 10885244
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-01-05
[patent_title] => Test pattern, test method for semiconductor device, and computer-implemented method for designing integrated circuit layout
[patent_app_type] => utility
[patent_app_number] => 16/739624
[patent_app_country] => US
[patent_app_date] => 2020-01-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 27
[patent_no_of_words] => 16357
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 189
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16739624
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/739624 | Test pattern, test method for semiconductor device, and computer-implemented method for designing integrated circuit layout | Jan 9, 2020 | Issued |
Array
(
[id] => 15869185
[patent_doc_number] => 20200141996
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-05-07
[patent_title] => OPTIMIZATION OF INTEGRATED CIRCUIT RELIABILITY
[patent_app_type] => utility
[patent_app_number] => 16/733573
[patent_app_country] => US
[patent_app_date] => 2020-01-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6343
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -7
[patent_words_short_claim] => 49
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16733573
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/733573 | Optimization of integrated circuit reliability | Jan 2, 2020 | Issued |
Array
(
[id] => 19539410
[patent_doc_number] => 12131967
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-10-29
[patent_title] => Electronic device package with board level reliability
[patent_app_type] => utility
[patent_app_number] => 16/725738
[patent_app_country] => US
[patent_app_date] => 2019-12-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 20
[patent_no_of_words] => 8145
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 93
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16725738
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/725738 | Electronic device package with board level reliability | Dec 22, 2019 | Issued |
Array
(
[id] => 15773661
[patent_doc_number] => 20200117848
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-04-16
[patent_title] => METHOD OF DETERMINING COLORABILITY OF A SEMICONDUCTOR DEVICE AND SYSTEM FOR IMPLEMENTING THE SAME
[patent_app_type] => utility
[patent_app_number] => 16/711112
[patent_app_country] => US
[patent_app_date] => 2019-12-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8626
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16711112
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/711112 | Method of determining colorability of a semiconductor device and system for implementing the same | Dec 10, 2019 | Issued |
Array
(
[id] => 17471422
[patent_doc_number] => 11277918
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-03-15
[patent_title] => Current redistribution in a printed circuit board
[patent_app_type] => utility
[patent_app_number] => 16/700198
[patent_app_country] => US
[patent_app_date] => 2019-12-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 5718
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 90
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16700198
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/700198 | Current redistribution in a printed circuit board | Dec 1, 2019 | Issued |
Array
(
[id] => 17478094
[patent_doc_number] => 20220085598
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-03-17
[patent_title] => BATTERY PROTECTION CIRCUIT, BATTERY PROTECTION BOARD, BATTERY, AND TERMINAL DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/416519
[patent_app_country] => US
[patent_app_date] => 2019-11-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 16933
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17416519
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/416519 | Battery protection circuit, battery protection board, battery, and terminal device | Nov 28, 2019 | Issued |
Array
(
[id] => 16307766
[patent_doc_number] => 10776560
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-09-15
[patent_title] => Mapping intermediate material properties to target properties to screen materials
[patent_app_type] => utility
[patent_app_number] => 16/691306
[patent_app_country] => US
[patent_app_date] => 2019-11-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 8629
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 225
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16691306
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/691306 | Mapping intermediate material properties to target properties to screen materials | Nov 20, 2019 | Issued |
Array
(
[id] => 18119588
[patent_doc_number] => 11550983
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-01-10
[patent_title] => Method for determining an electrical model of a string of photovoltaic modules, diagnostic method and device associated therewith
[patent_app_type] => utility
[patent_app_number] => 16/682807
[patent_app_country] => US
[patent_app_date] => 2019-11-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 14
[patent_no_of_words] => 11927
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 379
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16682807
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/682807 | Method for determining an electrical model of a string of photovoltaic modules, diagnostic method and device associated therewith | Nov 12, 2019 | Issued |
Array
(
[id] => 15592725
[patent_doc_number] => 20200072897
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-03-05
[patent_title] => OPTIMIZATION OF INTEGRATED CIRCUIT RELIABILITY
[patent_app_type] => utility
[patent_app_number] => 16/676635
[patent_app_country] => US
[patent_app_date] => 2019-11-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6343
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -6
[patent_words_short_claim] => 50
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16676635
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/676635 | Optimization of integrated circuit reliability | Nov 6, 2019 | Issued |
Array
(
[id] => 15595007
[patent_doc_number] => 20200074038
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-03-05
[patent_title] => MULTIPLE PATTERNING METHOD AND SYSTEM FOR IMPLEMENTING THE METHOD
[patent_app_type] => utility
[patent_app_number] => 16/676822
[patent_app_country] => US
[patent_app_date] => 2019-11-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8620
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 133
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16676822
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/676822 | Multiple patterning method and system for implementing the method | Nov 6, 2019 | Issued |
Array
(
[id] => 17233112
[patent_doc_number] => 20210359669
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-11-18
[patent_title] => DETECTING DEVICE AND SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/286091
[patent_app_country] => US
[patent_app_date] => 2019-10-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 30588
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -5
[patent_words_short_claim] => 252
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17286091
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/286091 | Detecting device and semiconductor device | Oct 16, 2019 | Issued |
Array
(
[id] => 15998517
[patent_doc_number] => 20200175129
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-06-04
[patent_title] => System on Chip (SOC) Current Profile Model for Integrated Voltage Regulator (IVR) Co-design
[patent_app_type] => utility
[patent_app_number] => 16/599823
[patent_app_country] => US
[patent_app_date] => 2019-10-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5586
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 34
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16599823
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/599823 | System on chip (SOC) current profile model for integrated voltage regulator (IVR) co-design | Oct 10, 2019 | Issued |
Array
(
[id] => 18154150
[patent_doc_number] => 11567125
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-01-31
[patent_title] => Injection device, semiconductor testing system and its testing method
[patent_app_type] => utility
[patent_app_number] => 16/597117
[patent_app_country] => US
[patent_app_date] => 2019-10-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 16
[patent_no_of_words] => 3836
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 194
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16597117
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/597117 | Injection device, semiconductor testing system and its testing method | Oct 8, 2019 | Issued |
Array
(
[id] => 18037955
[patent_doc_number] => 20220382171
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-12-01
[patent_title] => UNIVERSAL METROLOGY FILE, PROTOCOL, AND PROCESS FOR MASKLESS LITHOGRAPHY SYSTEMS
[patent_app_type] => utility
[patent_app_number] => 17/754072
[patent_app_country] => US
[patent_app_date] => 2019-10-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5906
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -12
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17754072
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/754072 | Universal metrology file, protocol, and process for maskless lithography systems | Oct 7, 2019 | Issued |
Array
(
[id] => 16751632
[patent_doc_number] => 20210103641
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-04-08
[patent_title] => ROUTING A CELL OF A SEMICONDUCTOR CHIP
[patent_app_type] => utility
[patent_app_number] => 16/595957
[patent_app_country] => US
[patent_app_date] => 2019-10-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5307
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16595957
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/595957 | Routing a cell of a semiconductor chip | Oct 7, 2019 | Issued |
Array
(
[id] => 16535565
[patent_doc_number] => 10878166
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2020-12-29
[patent_title] => Self-organized snapping for repeater planning
[patent_app_type] => utility
[patent_app_number] => 16/594914
[patent_app_country] => US
[patent_app_date] => 2019-10-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 17
[patent_no_of_words] => 8071
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 117
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16594914
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/594914 | Self-organized snapping for repeater planning | Oct 6, 2019 | Issued |
Array
(
[id] => 15967535
[patent_doc_number] => 20200167519
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-05-28
[patent_title] => MULTI-PATTERNING GRAPH REDUCTION AND CHECKING FLOW METHOD
[patent_app_type] => utility
[patent_app_number] => 16/587700
[patent_app_country] => US
[patent_app_date] => 2019-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12635
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 126
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16587700
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/587700 | Multi-patterning graph reduction and checking flow method | Sep 29, 2019 | Issued |
Array
(
[id] => 17023968
[patent_doc_number] => 20210247839
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-08-12
[patent_title] => ON-CHIP VOLTAGE ASSIGNMENT THROUGH PARTICLE SWARM OPTIMIZATION
[patent_app_type] => utility
[patent_app_number] => 17/271121
[patent_app_country] => US
[patent_app_date] => 2019-09-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13562
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 73
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17271121
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/271121 | On-chip voltage assignment through particle swarm optimization | Sep 2, 2019 | Issued |
Array
(
[id] => 16146273
[patent_doc_number] => 10706208
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2020-07-07
[patent_title] => Priority aware balancing of memory usage between geometry operation and file storage
[patent_app_type] => utility
[patent_app_number] => 16/542956
[patent_app_country] => US
[patent_app_date] => 2019-08-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 9
[patent_no_of_words] => 9306
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 260
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16542956
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/542956 | Priority aware balancing of memory usage between geometry operation and file storage | Aug 15, 2019 | Issued |
Array
(
[id] => 17136799
[patent_doc_number] => 11138356
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2021-10-05
[patent_title] => Dedicated reconfigurable IP for emulation-based power estimation
[patent_app_type] => utility
[patent_app_number] => 16/542289
[patent_app_country] => US
[patent_app_date] => 2019-08-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 7
[patent_no_of_words] => 4208
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 83
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16542289
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/542289 | Dedicated reconfigurable IP for emulation-based power estimation | Aug 14, 2019 | Issued |