Search

Brandon Bowers

Examiner (ID: 10602, Phone: (571)272-1888 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2825, 2851
Total Applications
889
Issued Applications
747
Pending Applications
56
Abandoned Applications
107

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15367803 [patent_doc_number] => 20200019666 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-16 [patent_title] => TAP CELLS [patent_app_type] => utility [patent_app_number] => 16/263841 [patent_app_country] => US [patent_app_date] => 2019-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5337 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16263841 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/263841
Method and system for latch-up prevention Jan 30, 2019 Issued
Array ( [id] => 14751155 [patent_doc_number] => 20190258751 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-22 [patent_title] => BUS WIRING SEARCHING METHOD AND INFORMATION PROCESSING APPARATUS [patent_app_type] => utility [patent_app_number] => 16/262038 [patent_app_country] => US [patent_app_date] => 2019-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11529 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16262038 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/262038
Bus wiring searching method and information processing apparatus Jan 29, 2019 Issued
Array ( [id] => 14782821 [patent_doc_number] => 20190266308 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-29 [patent_title] => INTEGRATED CIRCUIT DESIGN [patent_app_type] => utility [patent_app_number] => 16/261643 [patent_app_country] => US [patent_app_date] => 2019-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10519 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16261643 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/261643
Integrated circuit design Jan 29, 2019 Issued
Array ( [id] => 14689645 [patent_doc_number] => 20190243938 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-08 [patent_title] => CHIP DESIGN METHOD OF OPTIMIZING CIRCUIT PERFORMANCE ACCORDING TO CHANGE IN PVT OPERATION CONDITIONS [patent_app_type] => utility [patent_app_number] => 16/260890 [patent_app_country] => US [patent_app_date] => 2019-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7091 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16260890 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/260890
Chip design method of optimizing circuit performance according to change in PVT operation conditions Jan 28, 2019 Issued
Array ( [id] => 15386151 [patent_doc_number] => 10534258 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-14 [patent_title] => Structure design generation for fixing metal tip-to-tip across cell boundary [patent_app_type] => utility [patent_app_number] => 16/261264 [patent_app_country] => US [patent_app_date] => 2019-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 5244 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16261264 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/261264
Structure design generation for fixing metal tip-to-tip across cell boundary Jan 28, 2019 Issued
Array ( [id] => 14658221 [patent_doc_number] => 20190236239 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-01 [patent_title] => TIMING DRIVEN CELL SWAPPING [patent_app_type] => utility [patent_app_number] => 16/257822 [patent_app_country] => US [patent_app_date] => 2019-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4765 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16257822 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/257822
Timing driven cell swapping Jan 24, 2019 Issued
Array ( [id] => 14782819 [patent_doc_number] => 20190266307 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-29 [patent_title] => SYSTEM ON CHIP (SOC) BUILDER [patent_app_type] => utility [patent_app_number] => 16/258149 [patent_app_country] => US [patent_app_date] => 2019-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11151 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16258149 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/258149
System on chip (SoC) builder Jan 24, 2019 Issued
Array ( [id] => 14782827 [patent_doc_number] => 20190266311 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-29 [patent_title] => Pattern-Based Optical Proximity Correction [patent_app_type] => utility [patent_app_number] => 16/256518 [patent_app_country] => US [patent_app_date] => 2019-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9234 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16256518 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/256518
Pattern-based optical proximity correction Jan 23, 2019 Issued
Array ( [id] => 16209217 [patent_doc_number] => 20200242207 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-30 [patent_title] => TRACKING REFERENCES TO INFORMATION STORAGE RESOURCES IN A QUANTUM CIRCUIT [patent_app_type] => utility [patent_app_number] => 16/255999 [patent_app_country] => US [patent_app_date] => 2019-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5335 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16255999 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/255999
Tracking references to information storage resources in a quantum circuit Jan 23, 2019 Issued
Array ( [id] => 16046581 [patent_doc_number] => 10685164 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-06-16 [patent_title] => Circuit design routing based on parallel run length rules [patent_app_type] => utility [patent_app_number] => 16/239310 [patent_app_country] => US [patent_app_date] => 2019-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7630 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16239310 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/239310
Circuit design routing based on parallel run length rules Jan 2, 2019 Issued
Array ( [id] => 15358639 [patent_doc_number] => 10527932 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-07 [patent_title] => Structure design generation for fixing metal tip-to-tip across cell boundary [patent_app_type] => utility [patent_app_number] => 16/239165 [patent_app_country] => US [patent_app_date] => 2019-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 5257 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16239165 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/239165
Structure design generation for fixing metal tip-to-tip across cell boundary Jan 2, 2019 Issued
Array ( [id] => 15920123 [patent_doc_number] => 10657304 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-05-19 [patent_title] => Mapping logical qubits on a quantum circuit [patent_app_type] => utility [patent_app_number] => 16/238960 [patent_app_country] => US [patent_app_date] => 2019-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 14299 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16238960 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/238960
Mapping logical qubits on a quantum circuit Jan 2, 2019 Issued
Array ( [id] => 15855465 [patent_doc_number] => 10643020 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-05-05 [patent_title] => System and method to estimate a number of layers needed for routing a multi-die package [patent_app_type] => utility [patent_app_number] => 16/238257 [patent_app_country] => US [patent_app_date] => 2019-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 42 [patent_figures_cnt] => 46 [patent_no_of_words] => 17397 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16238257 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/238257
System and method to estimate a number of layers needed for routing a multi-die package Jan 1, 2019 Issued
Array ( [id] => 17772931 [patent_doc_number] => 11404889 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-02 [patent_title] => Power saving circuit for embedded battery applications [patent_app_type] => utility [patent_app_number] => 16/229846 [patent_app_country] => US [patent_app_date] => 2018-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 9795 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16229846 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/229846
Power saving circuit for embedded battery applications Dec 20, 2018 Issued
Array ( [id] => 16605432 [patent_doc_number] => 10906421 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-02 [patent_title] => Wireless automatic charging system for electric vehicles [patent_app_type] => utility [patent_app_number] => 16/228788 [patent_app_country] => US [patent_app_date] => 2018-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2110 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 406 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16228788 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/228788
Wireless automatic charging system for electric vehicles Dec 20, 2018 Issued
Array ( [id] => 16903548 [patent_doc_number] => 20210182464 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-17 [patent_title] => FPGA SYSTEM, PARTIAL RECONFIGURATION EXECUTION METHOD, AND STORAGE MEDIUM [patent_app_type] => utility [patent_app_number] => 16/771503 [patent_app_country] => US [patent_app_date] => 2018-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6557 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16771503 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/771503
FPGA system, partial reconfiguration execution method, and storage medium Dec 4, 2018 Issued
Array ( [id] => 18262338 [patent_doc_number] => 11610040 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-03-21 [patent_title] => System interconnect architecture using dynamic bitwise switch and low-latency input/output [patent_app_type] => utility [patent_app_number] => 16/209597 [patent_app_country] => US [patent_app_date] => 2018-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7658 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16209597 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/209597
System interconnect architecture using dynamic bitwise switch and low-latency input/output Dec 3, 2018 Issued
Array ( [id] => 17062241 [patent_doc_number] => 11106846 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-08-31 [patent_title] => Systems and methods for emulation data array compaction [patent_app_type] => utility [patent_app_number] => 16/208431 [patent_app_country] => US [patent_app_date] => 2018-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7786 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16208431 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/208431
Systems and methods for emulation data array compaction Dec 2, 2018 Issued
Array ( [id] => 15998515 [patent_doc_number] => 20200175128 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-04 [patent_title] => HARDWARE INCREMENTAL MODEL CHECKING VERIFICATION [patent_app_type] => utility [patent_app_number] => 16/203716 [patent_app_country] => US [patent_app_date] => 2018-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8520 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 314 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16203716 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/203716
Hardware incremental model checking verification Nov 28, 2018 Issued
Array ( [id] => 16355532 [patent_doc_number] => 10796044 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-06 [patent_title] => Interface connectivity for printed circuit board schematic [patent_app_type] => utility [patent_app_number] => 16/146749 [patent_app_country] => US [patent_app_date] => 2018-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4991 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16146749 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/146749
Interface connectivity for printed circuit board schematic Sep 27, 2018 Issued
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