Search

Brandon Bowers

Examiner (ID: 15542, Phone: (571)272-1888 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2825, 2851
Total Applications
903
Issued Applications
756
Pending Applications
52
Abandoned Applications
108

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15531061 [patent_doc_number] => 20200057836 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-20 [patent_title] => AUTONOMOUS PLACEMENT TO SATISFY SELF-ALIGNED DOUBLE PATTERNING CONSTRAINTS [patent_app_type] => utility [patent_app_number] => 16/103011 [patent_app_country] => US [patent_app_date] => 2018-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19056 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16103011 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/103011
Autonomous placement to satisfy self-aligned double patterning constraints Aug 13, 2018 Issued
Array ( [id] => 16337805 [patent_doc_number] => 10788759 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-29 [patent_title] => Prediction based chucking and lithography control optimization [patent_app_type] => utility [patent_app_number] => 16/049266 [patent_app_country] => US [patent_app_date] => 2018-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 3591 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16049266 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/049266
Prediction based chucking and lithography control optimization Jul 29, 2018 Issued
Array ( [id] => 13627597 [patent_doc_number] => 20180365350 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-20 [patent_title] => GENERATING CIRCUITS [patent_app_type] => utility [patent_app_number] => 16/001122 [patent_app_country] => US [patent_app_date] => 2018-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7244 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16001122 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/001122
GENERATING CIRCUITS Jun 5, 2018 Abandoned
Array ( [id] => 13411901 [patent_doc_number] => 20180257493 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-13 [patent_title] => ELECTRIC POWER RECEPTION DEVICE FOR VEHICLE, ELECTRIC POWER TRANSMISSION DEVICE, AND NON-CONTACT ELECTRIC POWER TRANSMISSION/RECEPTION SYSTEM [patent_app_type] => utility [patent_app_number] => 15/981293 [patent_app_country] => US [patent_app_date] => 2018-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17127 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15981293 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/981293
ELECTRIC POWER RECEPTION DEVICE FOR VEHICLE, ELECTRIC POWER TRANSMISSION DEVICE, AND NON-CONTACT ELECTRIC POWER TRANSMISSION/RECEPTION SYSTEM May 15, 2018 Abandoned
Array ( [id] => 15168091 [patent_doc_number] => 10489542 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-26 [patent_title] => Machine learning based post route path delay estimator from synthesis netlist [patent_app_type] => utility [patent_app_number] => 15/960833 [patent_app_country] => US [patent_app_date] => 2018-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5892 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15960833 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/960833
Machine learning based post route path delay estimator from synthesis netlist Apr 23, 2018 Issued
Array ( [id] => 15577175 [patent_doc_number] => 10578963 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-03 [patent_title] => Mask pattern generation based on fast marching method [patent_app_type] => utility [patent_app_number] => 15/959968 [patent_app_country] => US [patent_app_date] => 2018-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 12379 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15959968 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/959968
Mask pattern generation based on fast marching method Apr 22, 2018 Issued
Array ( [id] => 15028195 [patent_doc_number] => 20190325102 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-24 [patent_title] => CIRCUIT GENERATION BASED ON ZERO WIRE LOAD ASSERTIONS [patent_app_type] => utility [patent_app_number] => 15/957959 [patent_app_country] => US [patent_app_date] => 2018-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6967 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15957959 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/957959
Circuit generation based on zero wire load assertions Apr 19, 2018 Issued
Array ( [id] => 13317991 [patent_doc_number] => 20180210533 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-26 [patent_title] => VOLTAGE AND FREQUENCY BALANCING AT NOMINAL POINT [patent_app_type] => utility [patent_app_number] => 15/952558 [patent_app_country] => US [patent_app_date] => 2018-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8634 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 394 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15952558 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/952558
Voltage and frequency balancing at nominal point Apr 12, 2018 Issued
Array ( [id] => 13317993 [patent_doc_number] => 20180210534 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-26 [patent_title] => VOLTAGE AND FREQUENCY BALANCING AT NOMINAL POINT [patent_app_type] => utility [patent_app_number] => 15/952602 [patent_app_country] => US [patent_app_date] => 2018-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8637 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 405 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15952602 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/952602
Voltage and frequency balancing at nominal point Apr 12, 2018 Issued
Array ( [id] => 13481815 [patent_doc_number] => 20180292450 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-11 [patent_title] => Testing of Semiconductor Devices and Devices, and Designs Thereof [patent_app_type] => utility [patent_app_number] => 15/950972 [patent_app_country] => US [patent_app_date] => 2018-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7976 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15950972 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/950972
Testing of semiconductor devices and devices, and designs thereof Apr 10, 2018 Issued
Array ( [id] => 15313661 [patent_doc_number] => 10521537 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-31 [patent_title] => Method and system of generating layout [patent_app_type] => utility [patent_app_number] => 15/881383 [patent_app_country] => US [patent_app_date] => 2018-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 25 [patent_no_of_words] => 6075 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 388 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15881383 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/881383
Method and system of generating layout Jan 25, 2018 Issued
Array ( [id] => 18047009 [patent_doc_number] => 11520965 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-06 [patent_title] => Programmable device with pre-allocatable wiring structure [patent_app_type] => utility [patent_app_number] => 16/769164 [patent_app_country] => US [patent_app_date] => 2018-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 17 [patent_no_of_words] => 3992 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16769164 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/769164
Programmable device with pre-allocatable wiring structure Jan 7, 2018 Issued
Array ( [id] => 13144193 [patent_doc_number] => 10089431 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-02 [patent_title] => Tool for modular circuitboard design [patent_app_type] => utility [patent_app_number] => 15/816132 [patent_app_country] => US [patent_app_date] => 2017-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 8679 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 328 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15816132 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/816132
Tool for modular circuitboard design Nov 16, 2017 Issued
Array ( [id] => 12235184 [patent_doc_number] => 20180068048 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-08 [patent_title] => 'SIGNAL VIA POSITIONING IN A MULTI-LAYER CIRCUIT BOARD USING A GENETIC VIA PLACEMENT SOLVER' [patent_app_type] => utility [patent_app_number] => 15/813233 [patent_app_country] => US [patent_app_date] => 2017-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7162 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15813233 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/813233
Signal via positioning in a multi-layer circuit board using a genetic via placement solver Nov 14, 2017 Issued
Array ( [id] => 12242317 [patent_doc_number] => 20180075180 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-15 [patent_title] => 'SIGNAL VIA POSITIONING IN A MULTI-LAYER CIRCUIT BOARD USING A GENETIC VIA PLACEMENT SOLVER' [patent_app_type] => utility [patent_app_number] => 15/813236 [patent_app_country] => US [patent_app_date] => 2017-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7177 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15813236 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/813236
Signal via positioning in a multi-layer circuit board using a genetic via placement solver Nov 14, 2017 Issued
Array ( [id] => 14122319 [patent_doc_number] => 10248017 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-02 [patent_title] => Structure design generation for fixing metal tip-to-tip across cell boundary [patent_app_type] => utility [patent_app_number] => 15/811006 [patent_app_country] => US [patent_app_date] => 2017-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 5252 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15811006 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/811006
Structure design generation for fixing metal tip-to-tip across cell boundary Nov 12, 2017 Issued
Array ( [id] => 16065811 [patent_doc_number] => 10691858 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-06-23 [patent_title] => Filing vacant areas of an integrated circuit design [patent_app_type] => utility [patent_app_number] => 15/709376 [patent_app_country] => US [patent_app_date] => 2017-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 9188 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15709376 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/709376
Filing vacant areas of an integrated circuit design Sep 18, 2017 Issued
Array ( [id] => 16371459 [patent_doc_number] => 10803221 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-10-13 [patent_title] => Snap-to valid pattern system and method [patent_app_type] => utility [patent_app_number] => 15/695933 [patent_app_country] => US [patent_app_date] => 2017-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 2140 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15695933 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/695933
Snap-to valid pattern system and method Sep 4, 2017 Issued
Array ( [id] => 12094704 [patent_doc_number] => 20170351797 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-07 [patent_title] => 'Methods and Computer-Readable Media for Synthesizing a Multi-Corner Mesh-Based Clock Distribution Network for Multi-Voltage Domain and Clock Meshes and Integrated Circuits' [patent_app_type] => utility [patent_app_number] => 15/681735 [patent_app_country] => US [patent_app_date] => 2017-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5995 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15681735 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/681735
Methods and Computer-Readable Media for Synthesizing a Multi-Corner Mesh-Based Clock Distribution Network for Multi-Voltage Domain and Clock Meshes and Integrated Circuits Aug 20, 2017 Abandoned
Array ( [id] => 15412985 [patent_doc_number] => 20200026815 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-23 [patent_title] => OVER-THE-AIR HARDWARE UPDATE [patent_app_type] => utility [patent_app_number] => 16/320462 [patent_app_country] => US [patent_app_date] => 2017-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7878 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16320462 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/320462
Over-the-air hardware update Aug 8, 2017 Issued
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