Search

Brandon Bowers

Examiner (ID: 15542, Phone: (571)272-1888 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2825, 2851
Total Applications
903
Issued Applications
756
Pending Applications
52
Abandoned Applications
108

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11980940 [patent_doc_number] => 20170285094 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-05 [patent_title] => 'OPTIMIZATION OF INTEGRATED CIRCUIT RELIABILITY' [patent_app_type] => utility [patent_app_number] => 15/630415 [patent_app_country] => US [patent_app_date] => 2017-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6479 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15630415 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/630415
Optimization of integrated circuit reliability Jun 21, 2017 Issued
Array ( [id] => 14651593 [patent_doc_number] => 20190232925 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-01 [patent_title] => CHARGING STATION WITH MULTIPLE POWER SOURCES [patent_app_type] => utility [patent_app_number] => 16/312347 [patent_app_country] => US [patent_app_date] => 2017-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4033 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16312347 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/312347
Charging station with multiple power sources Jun 20, 2017 Issued
Array ( [id] => 16866530 [patent_doc_number] => 11025290 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-01 [patent_title] => Communication signal compensator [patent_app_type] => utility [patent_app_number] => 16/312984 [patent_app_country] => US [patent_app_date] => 2017-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 17 [patent_no_of_words] => 9544 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16312984 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/312984
Communication signal compensator Jun 19, 2017 Issued
Array ( [id] => 17254533 [patent_doc_number] => 11190040 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-30 [patent_title] => Shape of wireless power transmission coil and coil configuration method [patent_app_type] => utility [patent_app_number] => 16/312902 [patent_app_country] => US [patent_app_date] => 2017-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 13603 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16312902 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/312902
Shape of wireless power transmission coil and coil configuration method May 23, 2017 Issued
Array ( [id] => 13198731 [patent_doc_number] => 10114282 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-30 [patent_title] => Sampling for OPC building [patent_app_type] => utility [patent_app_number] => 15/474408 [patent_app_country] => US [patent_app_date] => 2017-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 3477 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15474408 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/474408
Sampling for OPC building Mar 29, 2017 Issued
Array ( [id] => 12967309 [patent_doc_number] => 09875331 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-01-23 [patent_title] => Signal via positioning in a multi-layer circuit board using a genetic via placement solver [patent_app_type] => utility [patent_app_number] => 15/430970 [patent_app_country] => US [patent_app_date] => 2017-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 6671 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15430970 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/430970
Signal via positioning in a multi-layer circuit board using a genetic via placement solver Feb 12, 2017 Issued
Array ( [id] => 17165200 [patent_doc_number] => 11151300 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-10-19 [patent_title] => Integrated routing assembly and system using same [patent_app_type] => utility [patent_app_number] => 16/070636 [patent_app_country] => US [patent_app_date] => 2017-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 37 [patent_no_of_words] => 6553 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16070636 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/070636
Integrated routing assembly and system using same Jan 18, 2017 Issued
Array ( [id] => 13172427 [patent_doc_number] => 10102330 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-10-16 [patent_title] => Method for automatically determining proposed standard cell design conformance based upon template constraints [patent_app_type] => utility [patent_app_number] => 15/395709 [patent_app_country] => US [patent_app_date] => 2016-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 2241 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 396 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15395709 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/395709
Method for automatically determining proposed standard cell design conformance based upon template constraints Dec 29, 2016 Issued
Array ( [id] => 12496092 [patent_doc_number] => 09996649 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-06-12 [patent_title] => On the fly netlist compression in power analysis [patent_app_type] => utility [patent_app_number] => 15/384447 [patent_app_country] => US [patent_app_date] => 2016-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 12948 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 908 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15384447 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/384447
On the fly netlist compression in power analysis Dec 19, 2016 Issued
Array ( [id] => 12633234 [patent_doc_number] => 20180102908 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-12 [patent_title] => FINE GRAIN RECONFIGURABLE BUILDING BLOCK FOR IC PROTECTION AND OBFUSCATION [patent_app_type] => utility [patent_app_number] => 15/290672 [patent_app_country] => US [patent_app_date] => 2016-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5576 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15290672 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/290672
FINE GRAIN RECONFIGURABLE BUILDING BLOCK FOR IC PROTECTION AND OBFUSCATION Oct 10, 2016 Abandoned
Array ( [id] => 12628143 [patent_doc_number] => 20180101211 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-12 [patent_title] => VOLTAGE AND FREQUENCY BALANCING AT NOMINAL POINT [patent_app_type] => utility [patent_app_number] => 15/286903 [patent_app_country] => US [patent_app_date] => 2016-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8606 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15286903 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/286903
Voltage and frequency balancing at nominal point Oct 5, 2016 Issued
Array ( [id] => 13682467 [patent_doc_number] => 20160379970 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-29 [patent_title] => DECOUPLING CAPACITOR CELL, CELL-BASED IC, AND PORTABLE DEVICE [patent_app_type] => utility [patent_app_number] => 15/262921 [patent_app_country] => US [patent_app_date] => 2016-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4473 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15262921 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/262921
DECOUPLING CAPACITOR CELL, CELL-BASED IC, AND PORTABLE DEVICE Sep 11, 2016 Abandoned
Array ( [id] => 11501844 [patent_doc_number] => 20170076029 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-16 [patent_title] => 'SYSTEM AND METHOD FOR SYSTEM-LEVEL PARAMETER ESTIMATION' [patent_app_type] => utility [patent_app_number] => 15/260143 [patent_app_country] => US [patent_app_date] => 2016-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6591 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15260143 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/260143
System and method for system-level parameter estimation Sep 7, 2016 Issued
Array ( [id] => 15168101 [patent_doc_number] => 10489547 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-26 [patent_title] => Multiple patterning method, system for implementing the method and layout formed [patent_app_type] => utility [patent_app_number] => 15/259559 [patent_app_country] => US [patent_app_date] => 2016-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 8007 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15259559 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/259559
Multiple patterning method, system for implementing the method and layout formed Sep 7, 2016 Issued
Array ( [id] => 11693436 [patent_doc_number] => 20170169153 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-15 [patent_title] => 'TEST PATTERN, TEST METHOD FOR SEMICONDUCTOR DEVICE, AND COMPUTER-IMPLEMENTED METHOD FOR DESIGNING INTEGRATED CIRCUIT LAYOUT' [patent_app_type] => utility [patent_app_number] => 15/259673 [patent_app_country] => US [patent_app_date] => 2016-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 16745 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15259673 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/259673
Test pattern, test method for semiconductor device, and computer-implemented designing integrated circuit layout Sep 7, 2016 Issued
Array ( [id] => 11494588 [patent_doc_number] => 20170068772 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-09 [patent_title] => 'SYSTEM FOR OPTIMIZING POWER LEAKAGE AND TIMING DELAY IN AN INTEGRATED CIRCUIT BASED ON A COST FACTOR OF REPLACING CELLS' [patent_app_type] => utility [patent_app_number] => 15/258923 [patent_app_country] => US [patent_app_date] => 2016-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6981 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15258923 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/258923
SYSTEM FOR OPTIMIZING POWER LEAKAGE AND TIMING DELAY IN AN INTEGRATED CIRCUIT BASED ON A COST FACTOR OF REPLACING CELLS Sep 6, 2016 Abandoned
Array ( [id] => 12235186 [patent_doc_number] => 20180068050 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-08 [patent_title] => 'SYSTEM FOR AND METHOD OF MANUFACTURING A LAYOUT DESIGN OF AN INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 15/258932 [patent_app_country] => US [patent_app_date] => 2016-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 16724 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15258932 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/258932
System for and method of manufacturing a layout design of an integrated circuit Sep 6, 2016 Issued
Array ( [id] => 13686141 [patent_doc_number] => 20160381807 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-29 [patent_title] => Current Redistribution in a Printed Circuit Board [patent_app_type] => utility [patent_app_number] => 15/258472 [patent_app_country] => US [patent_app_date] => 2016-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5662 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15258472 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/258472
Current redistribution in a printed circuit board Sep 6, 2016 Issued
Array ( [id] => 11591954 [patent_doc_number] => 20170116365 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-04-27 [patent_title] => 'INTEGRATED CIRCUIT USING STANDARD CELLS FROM TWO OR MORE LIBRARIES' [patent_app_type] => utility [patent_app_number] => 15/256592 [patent_app_country] => US [patent_app_date] => 2016-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3258 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15256592 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/256592
INTEGRATED CIRCUIT USING STANDARD CELLS FROM TWO OR MORE LIBRARIES Sep 3, 2016 Abandoned
Array ( [id] => 12235187 [patent_doc_number] => 20180068049 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-08 [patent_title] => 'MULTI-PATTERNING GRAPH REDUCTION AND CHECKING FLOW METHOD' [patent_app_type] => utility [patent_app_number] => 15/255489 [patent_app_country] => US [patent_app_date] => 2016-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 13811 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15255489 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/255489
Multi-patterning graph reduction and checking flow method Sep 1, 2016 Issued
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