Search

Brandon Bowers

Examiner (ID: 15542, Phone: (571)272-1888 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2825, 2851
Total Applications
903
Issued Applications
756
Pending Applications
52
Abandoned Applications
108

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 12235187 [patent_doc_number] => 20180068049 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-08 [patent_title] => 'MULTI-PATTERNING GRAPH REDUCTION AND CHECKING FLOW METHOD' [patent_app_type] => utility [patent_app_number] => 15/255489 [patent_app_country] => US [patent_app_date] => 2016-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 13811 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15255489 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/255489
Multi-patterning graph reduction and checking flow method Sep 1, 2016 Issued
Array ( [id] => 11339990 [patent_doc_number] => 20160365746 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-15 [patent_title] => 'DEVICE FOR WIRELESS CHARGING HAVING A PLURALITY OF WIRELESS CHARGING PROTOCOLS' [patent_app_type] => utility [patent_app_number] => 15/247189 [patent_app_country] => US [patent_app_date] => 2016-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5331 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15247189 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/247189
DEVICE FOR WIRELESS CHARGING HAVING A PLURALITY OF WIRELESS CHARGING PROTOCOLS Aug 24, 2016 Abandoned
Array ( [id] => 11069233 [patent_doc_number] => 20160266197 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-15 [patent_title] => 'Testing of Semiconductor Devices and Devices, and Designs Thereof' [patent_app_type] => utility [patent_app_number] => 15/162679 [patent_app_country] => US [patent_app_date] => 2016-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 7648 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15162679 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/162679
Testing of semiconductor devices and devices, and designs thereof May 23, 2016 Issued
Array ( [id] => 11062032 [patent_doc_number] => 20160258994 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-08 [patent_title] => 'OPTIMIZATION OF INTEGRATED CIRCUIT RELIABILITY' [patent_app_type] => utility [patent_app_number] => 15/155518 [patent_app_country] => US [patent_app_date] => 2016-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6479 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15155518 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/155518
Optimization of integrated circuit reliability May 15, 2016 Issued
Array ( [id] => 12514263 [patent_doc_number] => 10002220 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-06-19 [patent_title] => On the fly netlist compression in power analysis [patent_app_type] => utility [patent_app_number] => 15/139525 [patent_app_country] => US [patent_app_date] => 2016-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 12943 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 415 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15139525 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/139525
On the fly netlist compression in power analysis Apr 26, 2016 Issued
Array ( [id] => 12026039 [patent_doc_number] => 20170316139 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-02 [patent_title] => 'SIGNAL VIA POSITIONING IN A MULTI-LAYER CIRCUIT BOARD USING A GENETIC VIA PLACEMENT SOLVER' [patent_app_type] => utility [patent_app_number] => 15/139653 [patent_app_country] => US [patent_app_date] => 2016-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7128 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15139653 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/139653
Signal via positioning in a multi-layer circuit board using a genetic via placement solver Apr 26, 2016 Issued
Array ( [id] => 14669911 [patent_doc_number] => 10372857 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-06 [patent_title] => Determining parameters of PCB structures [patent_app_type] => utility [patent_app_number] => 15/138858 [patent_app_country] => US [patent_app_date] => 2016-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2999 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15138858 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/138858
Determining parameters of PCB structures Apr 25, 2016 Issued
Array ( [id] => 12004481 [patent_doc_number] => 20170308637 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-26 [patent_title] => 'PROBABILISTIC THERMAL HOTSPOT ACCOMMODATION' [patent_app_type] => utility [patent_app_number] => 15/136512 [patent_app_country] => US [patent_app_date] => 2016-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 10608 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15136512 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/136512
PROBABILISTIC THERMAL HOTSPOT ACCOMMODATION Apr 21, 2016 Abandoned
Array ( [id] => 14767169 [patent_doc_number] => 10394981 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-08-27 [patent_title] => Techniques for testing programmable interconnect resources [patent_app_type] => utility [patent_app_number] => 15/135113 [patent_app_country] => US [patent_app_date] => 2016-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8521 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15135113 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/135113
Techniques for testing programmable interconnect resources Apr 20, 2016 Issued
Array ( [id] => 12114447 [patent_doc_number] => 09870441 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-01-16 [patent_title] => 'Snap-to valid pattern system and method' [patent_app_type] => utility [patent_app_number] => 15/073493 [patent_app_country] => US [patent_app_date] => 2016-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 2173 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15073493 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/073493
Snap-to valid pattern system and method Mar 16, 2016 Issued
Array ( [id] => 10991829 [patent_doc_number] => 20160188774 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-30 [patent_title] => 'Circuit Design and Optimization' [patent_app_type] => utility [patent_app_number] => 15/063479 [patent_app_country] => US [patent_app_date] => 2016-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 8422 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15063479 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/063479
Circuit Design and Optimization Mar 6, 2016 Abandoned
Array ( [id] => 10991840 [patent_doc_number] => 20160188786 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-30 [patent_title] => 'TECHNOLOGY FOR TEMPERATURE SENSITIVE COMPONENTS IN THERMAL PROCESSING' [patent_app_type] => utility [patent_app_number] => 15/062196 [patent_app_country] => US [patent_app_date] => 2016-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 10063 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15062196 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/062196
Technology for temperature sensitive components in thermal processing Mar 6, 2016 Issued
Array ( [id] => 10809545 [patent_doc_number] => 20160155704 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-02 [patent_title] => 'DIFFERENT SCALING RATIO IN FEOL / MOL/ BEOL' [patent_app_type] => utility [patent_app_number] => 15/016448 [patent_app_country] => US [patent_app_date] => 2016-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4631 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15016448 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/016448
Different scaling ratio in FEOL/ MOL/ BEOL Feb 4, 2016 Issued
Array ( [id] => 12937354 [patent_doc_number] => 09831700 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-11-28 [patent_title] => Mitigating premature wear out of a rechargeable battery [patent_app_type] => utility [patent_app_number] => 14/993013 [patent_app_country] => US [patent_app_date] => 2016-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 8883 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14993013 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/993013
Mitigating premature wear out of a rechargeable battery Jan 10, 2016 Issued
Array ( [id] => 11745884 [patent_doc_number] => 20170199957 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-13 [patent_title] => 'METHOD OF DETERMINING COLORABILITY OF A SEMICONDUCTOR DEVICE AND SYSTEM FOR IMPLEMENTING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/990446 [patent_app_country] => US [patent_app_date] => 2016-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8339 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14990446 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/990446
Method of determining colorability of a semiconductor device and system for implementing the same Jan 6, 2016 Issued
Array ( [id] => 11078249 [patent_doc_number] => 20160275213 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-22 [patent_title] => 'BEHAVIORAL SYNTHESIS METHOD, BEHAVIORAL SYNTHESIS DEVICE AND COMPUTER READABLE RECORDING MEDIUM STORING BEHAVIORAL SYNTHESIS PROGRAM' [patent_app_type] => utility [patent_app_number] => 14/990292 [patent_app_country] => US [patent_app_date] => 2016-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 5103 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14990292 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/990292
BEHAVIORAL SYNTHESIS METHOD, BEHAVIORAL SYNTHESIS DEVICE AND COMPUTER READABLE RECORDING MEDIUM STORING BEHAVIORAL SYNTHESIS PROGRAM Jan 6, 2016 Abandoned
Array ( [id] => 13918965 [patent_doc_number] => 10203596 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-12 [patent_title] => Method of filtering overlay data by field [patent_app_type] => utility [patent_app_number] => 14/989765 [patent_app_country] => US [patent_app_date] => 2016-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2943 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14989765 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/989765
Method of filtering overlay data by field Jan 5, 2016 Issued
Array ( [id] => 14150043 [patent_doc_number] => 10255403 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-04-09 [patent_title] => Method and apparatus for concurrently extracting and validating timing models for different views in multi-mode multi-corner designs [patent_app_type] => utility [patent_app_number] => 14/988808 [patent_app_country] => US [patent_app_date] => 2016-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 13001 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 244 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14988808 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/988808
Method and apparatus for concurrently extracting and validating timing models for different views in multi-mode multi-corner designs Jan 5, 2016 Issued
Array ( [id] => 15059525 [patent_doc_number] => 10460069 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-10-29 [patent_title] => Functional reactive PCells [patent_app_type] => utility [patent_app_number] => 14/984844 [patent_app_country] => US [patent_app_date] => 2015-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 14009 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14984844 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/984844
Functional reactive PCells Dec 29, 2015 Issued
Array ( [id] => 10983070 [patent_doc_number] => 20160180014 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-23 [patent_title] => 'ENHANCING INTEGRATED CIRCUIT NOISE PERFORMANCE' [patent_app_type] => utility [patent_app_number] => 14/967433 [patent_app_country] => US [patent_app_date] => 2015-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6281 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14967433 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/967433
Enhancing integrated circuit noise performance Dec 13, 2015 Issued
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