Search

Brandon Bowers

Examiner (ID: 15542, Phone: (571)272-1888 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2825, 2851
Total Applications
903
Issued Applications
756
Pending Applications
52
Abandoned Applications
108

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 13055569 [patent_doc_number] => 10049177 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-08-14 [patent_title] => Circuits for and methods of reducing power consumed by routing clock signals in an integrated [patent_app_type] => utility [patent_app_number] => 14/792953 [patent_app_country] => US [patent_app_date] => 2015-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 24 [patent_no_of_words] => 11872 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14792953 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/792953
Circuits for and methods of reducing power consumed by routing clock signals in an integrated Jul 6, 2015 Issued
Array ( [id] => 12256190 [patent_doc_number] => 09928336 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-03-27 [patent_title] => 'Methods, systems, and articles of manufacture for simplifying an electronic design for verification by domain reduction' [patent_app_type] => utility [patent_app_number] => 14/793723 [patent_app_country] => US [patent_app_date] => 2015-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 24 [patent_no_of_words] => 13347 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14793723 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/793723
Methods, systems, and articles of manufacture for simplifying an electronic design for verification by domain reduction Jul 6, 2015 Issued
Array ( [id] => 12332508 [patent_doc_number] => 09946831 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-04-17 [patent_title] => Method for closed loop testing of ASICs with image sensors in emulation [patent_app_type] => utility [patent_app_number] => 14/793671 [patent_app_country] => US [patent_app_date] => 2015-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4575 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14793671 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/793671
Method for closed loop testing of ASICs with image sensors in emulation Jul 6, 2015 Issued
Array ( [id] => 11049955 [patent_doc_number] => 20160246914 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-25 [patent_title] => 'PRINTED CIRCUIT BOARD DESIGN DEVICE' [patent_app_type] => utility [patent_app_number] => 14/793511 [patent_app_country] => US [patent_app_date] => 2015-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2996 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14793511 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/793511
PRINTED CIRCUIT BOARD DESIGN DEVICE Jul 6, 2015 Abandoned
Array ( [id] => 11385103 [patent_doc_number] => 20170011158 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-01-12 [patent_title] => 'CROSS-HIERARCHY INTERCONNECT ADJUSTMENT FOR POWER RECOVERY' [patent_app_type] => utility [patent_app_number] => 14/793097 [patent_app_country] => US [patent_app_date] => 2015-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4978 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14793097 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/793097
Cross-hierarchy interconnect adjustment for power recovery Jul 6, 2015 Issued
Array ( [id] => 11716481 [patent_doc_number] => 20170184979 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-29 [patent_title] => 'OPTIMIZATION OF ASSIST FEATURES AND SOURCE' [patent_app_type] => utility [patent_app_number] => 15/325428 [patent_app_country] => US [patent_app_date] => 2015-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 33 [patent_no_of_words] => 22021 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15325428 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/325428
Optimization of assist features and source Jun 28, 2015 Issued
Array ( [id] => 10384299 [patent_doc_number] => 20150269306 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-24 [patent_title] => 'SYSTEM AND METHODS FOR OPC MODEL ACCURACY MANAGEMENT AND DISPOSITION' [patent_app_type] => utility [patent_app_number] => 14/730244 [patent_app_country] => US [patent_app_date] => 2015-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4084 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14730244 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/730244
System and methods for OPC model accuracy management and disposition Jun 3, 2015 Issued
Array ( [id] => 11832250 [patent_doc_number] => 09729000 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-08 [patent_title] => 'Wireless power multi-charging method and power transmitter' [patent_app_type] => utility [patent_app_number] => 14/711333 [patent_app_country] => US [patent_app_date] => 2015-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 6097 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14711333 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/711333
Wireless power multi-charging method and power transmitter May 12, 2015 Issued
Array ( [id] => 11903645 [patent_doc_number] => 09773079 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-09-26 [patent_title] => 'Methods and computer-readable media for synthesizing a multi-corner mesh-based clock distribution network for multi-voltage domain and clock meshes and integrated circuits' [patent_app_type] => utility [patent_app_number] => 14/697864 [patent_app_country] => US [patent_app_date] => 2015-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5969 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14697864 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/697864
Methods and computer-readable media for synthesizing a multi-corner mesh-based clock distribution network for multi-voltage domain and clock meshes and integrated circuits Apr 27, 2015 Issued
Array ( [id] => 11659306 [patent_doc_number] => 09672309 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-06-06 [patent_title] => 'Method for generating layout pattern' [patent_app_type] => utility [patent_app_number] => 14/696498 [patent_app_country] => US [patent_app_date] => 2015-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4698 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14696498 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/696498
Method for generating layout pattern Apr 26, 2015 Issued
Array ( [id] => 11117263 [patent_doc_number] => 20160314237 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-27 [patent_title] => 'METHOD AND SYSTEM FOR DETECTING DEFECTS OF WAFER BY WAFER SORT' [patent_app_type] => utility [patent_app_number] => 14/694017 [patent_app_country] => US [patent_app_date] => 2015-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3966 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14694017 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/694017
Method and system for detecting defects of wafer by wafer sort Apr 22, 2015 Issued
Array ( [id] => 10446972 [patent_doc_number] => 20150331986 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-19 [patent_title] => 'INSULATION DISTANCE CHECK DEVICE' [patent_app_type] => utility [patent_app_number] => 14/694289 [patent_app_country] => US [patent_app_date] => 2015-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 5182 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14694289 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/694289
Insulation distance check device Apr 22, 2015 Issued
Array ( [id] => 11042645 [patent_doc_number] => 20160239601 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-18 [patent_title] => 'MASK DATA GENERATION SYSTEM, MASK DATA GENERATION METHOD, AND RECORDING MEDIUM' [patent_app_type] => utility [patent_app_number] => 14/694090 [patent_app_country] => US [patent_app_date] => 2015-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 12084 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14694090 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/694090
Mask data generation system, mask data generation method, and recording medium Apr 22, 2015 Issued
Array ( [id] => 10815681 [patent_doc_number] => 20160161841 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-09 [patent_title] => 'SAMPLING FOR OPC MODEL BUILDING' [patent_app_type] => utility [patent_app_number] => 14/678008 [patent_app_country] => US [patent_app_date] => 2015-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3461 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14678008 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/678008
Sampling for OPC model building Apr 2, 2015 Issued
Array ( [id] => 11095375 [patent_doc_number] => 20160292344 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-06 [patent_title] => 'SIGNAL INTEGRITY DELAY UTILIZING A WINDOW BUMP-BASED AGGRESSOR ALIGNMENT SCHEME' [patent_app_type] => utility [patent_app_number] => 14/678788 [patent_app_country] => US [patent_app_date] => 2015-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8152 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14678788 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/678788
Signal integrity delay utilizing a window bump-based aggressor alignment scheme Apr 2, 2015 Issued
Array ( [id] => 12146859 [patent_doc_number] => 09881112 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-01-30 [patent_title] => 'Vectorless dynamic power estimation for sequential circuits' [patent_app_type] => utility [patent_app_number] => 14/677868 [patent_app_country] => US [patent_app_date] => 2015-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 12421 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14677868 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/677868
Vectorless dynamic power estimation for sequential circuits Apr 1, 2015 Issued
Array ( [id] => 12011838 [patent_doc_number] => 09805157 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-10-31 [patent_title] => 'Decoupling capacitor analysis techniques' [patent_app_type] => utility [patent_app_number] => 14/660710 [patent_app_country] => US [patent_app_date] => 2015-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5023 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14660710 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/660710
Decoupling capacitor analysis techniques Mar 16, 2015 Issued
Array ( [id] => 10384291 [patent_doc_number] => 20150269298 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-24 [patent_title] => 'NETWORK FLOW BASED FRAMEWORK FOR CLOCK TREE OPTIMIZATION' [patent_app_type] => utility [patent_app_number] => 14/660535 [patent_app_country] => US [patent_app_date] => 2015-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6164 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14660535 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/660535
Network flow based framework for clock tree optimization Mar 16, 2015 Issued
Array ( [id] => 11465020 [patent_doc_number] => 09581644 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-02-28 [patent_title] => 'Digital IC simulation' [patent_app_type] => utility [patent_app_number] => 14/656790 [patent_app_country] => US [patent_app_date] => 2015-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 7251 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14656790 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/656790
Digital IC simulation Mar 12, 2015 Issued
Array ( [id] => 11042644 [patent_doc_number] => 20160239600 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-18 [patent_title] => 'Prediction Based Chucking and Lithography Control Optimization' [patent_app_type] => utility [patent_app_number] => 14/656422 [patent_app_country] => US [patent_app_date] => 2015-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3604 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14656422 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/656422
Prediction based chucking and lithography control optimization Mar 11, 2015 Issued
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