Search

Brandon Bowers

Examiner (ID: 10602, Phone: (571)272-1888 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2825, 2851
Total Applications
889
Issued Applications
747
Pending Applications
56
Abandoned Applications
107

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18651922 [patent_doc_number] => 20230297758 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-21 [patent_title] => TIMING DRIVEN CELL SWAPPING [patent_app_type] => utility [patent_app_number] => 18/322156 [patent_app_country] => US [patent_app_date] => 2023-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4821 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18322156 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/322156
Timing driven cell swapping May 22, 2023 Issued
Array ( [id] => 18586036 [patent_doc_number] => 20230268301 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-24 [patent_title] => METHOD AND SYSTEM FOR VERIFYING INTEGRATED CIRCUIT STACK HAVING PHOTONIC DEVICE [patent_app_type] => utility [patent_app_number] => 18/306994 [patent_app_country] => US [patent_app_date] => 2023-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6248 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18306994 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/306994
Method and system for verifying integrated circuit stack having photonic device Apr 24, 2023 Issued
Array ( [id] => 19355984 [patent_doc_number] => 12056432 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-06 [patent_title] => Pin modification for standard cells [patent_app_type] => utility [patent_app_number] => 18/300142 [patent_app_country] => US [patent_app_date] => 2023-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6487 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18300142 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/300142
Pin modification for standard cells Apr 12, 2023 Issued
Array ( [id] => 19229712 [patent_doc_number] => 12009356 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-11 [patent_title] => Integrated circuit and method of forming the same [patent_app_type] => utility [patent_app_number] => 18/190703 [patent_app_country] => US [patent_app_date] => 2023-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 19293 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18190703 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/190703
Integrated circuit and method of forming the same Mar 26, 2023 Issued
Array ( [id] => 18532165 [patent_doc_number] => 20230237237 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-27 [patent_title] => METHOD AND SYSTEM FOR LATCH-UP PREVENTION [patent_app_type] => utility [patent_app_number] => 18/190309 [patent_app_country] => US [patent_app_date] => 2023-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5395 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18190309 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/190309
Method and system for latch-up prevention Mar 26, 2023 Issued
Array ( [id] => 18551563 [patent_doc_number] => 20230249568 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-10 [patent_title] => SYSTEM AND METHOD FOR AUTONOMOUSLY CHARGING ELECTRIC VEHICLES [patent_app_type] => utility [patent_app_number] => 18/179837 [patent_app_country] => US [patent_app_date] => 2023-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16922 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18179837 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/179837
SYSTEM AND METHOD FOR AUTONOMOUSLY CHARGING ELECTRIC VEHICLES Mar 6, 2023 Abandoned
Array ( [id] => 18471672 [patent_doc_number] => 20230205958 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-29 [patent_title] => Attribute-Point-Based Timing Constraint Formal Verification [patent_app_type] => utility [patent_app_number] => 18/176717 [patent_app_country] => US [patent_app_date] => 2023-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5628 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18176717 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/176717
Attribute-point-based timing constraint formal verification Feb 28, 2023 Issued
Array ( [id] => 19384638 [patent_doc_number] => 20240274508 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-15 [patent_title] => SEMICONDUCTOR STRUCTURE WITH ENHANCED VOLTAGE STRESS CONTROL AND METHOD OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/169855 [patent_app_country] => US [patent_app_date] => 2023-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10686 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18169855 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/169855
SEMICONDUCTOR STRUCTURE WITH ENHANCED VOLTAGE STRESS CONTROL AND METHOD OF FORMING THE SAME Feb 14, 2023 Pending
Array ( [id] => 19363148 [patent_doc_number] => 20240265182 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-08 [patent_title] => ELECTROSTATICS-BASED GLOBAL PLACEMENT OF CIRCUIT DESIGNS HAVING OVERLAPPING REGION CONSTRAINTS [patent_app_type] => utility [patent_app_number] => 18/105605 [patent_app_country] => US [patent_app_date] => 2023-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6363 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18105605 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/105605
ELECTROSTATICS-BASED GLOBAL PLACEMENT OF CIRCUIT DESIGNS HAVING OVERLAPPING REGION CONSTRAINTS Feb 2, 2023 Pending
Array ( [id] => 19347790 [patent_doc_number] => 20240256754 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-01 [patent_title] => METHOD AND SYSTEM FOR USE WITH AN ELECTRONIC DESIGN AUTOMATION (EDA) TOOL TO OPTIMIZE CLOCK SCHEDULING [patent_app_type] => utility [patent_app_number] => 18/103859 [patent_app_country] => US [patent_app_date] => 2023-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4015 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18103859 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/103859
METHOD AND SYSTEM FOR USE WITH AN ELECTRONIC DESIGN AUTOMATION (EDA) TOOL TO OPTIMIZE CLOCK SCHEDULING Jan 30, 2023 Pending
Array ( [id] => 18651916 [patent_doc_number] => 20230297752 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-21 [patent_title] => INTEGRATED CIRCUITS INCLUDING ABUTTED BLOCKS AND METHODS OF DESIGNING LAYOUTS OF THE INTEGRATED CIRCUITS [patent_app_type] => utility [patent_app_number] => 18/162120 [patent_app_country] => US [patent_app_date] => 2023-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9700 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18162120 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/162120
INTEGRATED CIRCUITS INCLUDING ABUTTED BLOCKS AND METHODS OF DESIGNING LAYOUTS OF THE INTEGRATED CIRCUITS Jan 30, 2023 Pending
Array ( [id] => 18651916 [patent_doc_number] => 20230297752 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-21 [patent_title] => INTEGRATED CIRCUITS INCLUDING ABUTTED BLOCKS AND METHODS OF DESIGNING LAYOUTS OF THE INTEGRATED CIRCUITS [patent_app_type] => utility [patent_app_number] => 18/162120 [patent_app_country] => US [patent_app_date] => 2023-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9700 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18162120 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/162120
INTEGRATED CIRCUITS INCLUDING ABUTTED BLOCKS AND METHODS OF DESIGNING LAYOUTS OF THE INTEGRATED CIRCUITS Jan 30, 2023 Pending
Array ( [id] => 18392737 [patent_doc_number] => 20230160957 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-25 [patent_title] => METHODS AND SYSTEMS FOR FAULT INJECTION TESTING OF AN INTEGRATED CIRCUIT HARDWARE DESIGN [patent_app_type] => utility [patent_app_number] => 18/101085 [patent_app_country] => US [patent_app_date] => 2023-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16107 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18101085 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/101085
Methods and systems for fault injection testing of an integrated circuit hardware design Jan 23, 2023 Issued
Array ( [id] => 19911800 [patent_doc_number] => 12288011 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-29 [patent_title] => Methods and systems for streaming buffer numerical propagation [patent_app_type] => utility [patent_app_number] => 18/157720 [patent_app_country] => US [patent_app_date] => 2023-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4565 [patent_no_of_claims] => 60 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18157720 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/157720
Methods and systems for streaming buffer numerical propagation Jan 19, 2023 Issued
Array ( [id] => 19320469 [patent_doc_number] => 20240242013 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-18 [patent_title] => TRUSTED PARAMETERIZED CELLS (PCELLS) ON BLOCKCHAIN [patent_app_type] => utility [patent_app_number] => 18/153799 [patent_app_country] => US [patent_app_date] => 2023-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4037 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18153799 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/153799
TRUSTED PARAMETERIZED CELLS (PCELLS) ON BLOCKCHAIN Jan 11, 2023 Pending
Array ( [id] => 19320469 [patent_doc_number] => 20240242013 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-18 [patent_title] => TRUSTED PARAMETERIZED CELLS (PCELLS) ON BLOCKCHAIN [patent_app_type] => utility [patent_app_number] => 18/153799 [patent_app_country] => US [patent_app_date] => 2023-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4037 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18153799 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/153799
TRUSTED PARAMETERIZED CELLS (PCELLS) ON BLOCKCHAIN Jan 11, 2023 Pending
Array ( [id] => 18361262 [patent_doc_number] => 20230142853 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-11 [patent_title] => DEVICES WITH TRACK-BASED FILL (TBF) METAL PATTERNING [patent_app_type] => utility [patent_app_number] => 18/152983 [patent_app_country] => US [patent_app_date] => 2023-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9262 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18152983 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/152983
DEVICES WITH TRACK-BASED FILL (TBF) METAL PATTERNING Jan 10, 2023 Pending
Array ( [id] => 19363147 [patent_doc_number] => 20240265181 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-08 [patent_title] => OPTIMIZATION METHOD FOR DIGITAL INTEGRATED CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/571727 [patent_app_country] => US [patent_app_date] => 2023-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4931 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 496 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18571727 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/571727
Optimization method for digital integrated circuit Jan 2, 2023 Issued
Array ( [id] => 18454886 [patent_doc_number] => 20230196167 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-22 [patent_title] => BACK GRID FOR QUANTUM DEVICE [patent_app_type] => utility [patent_app_number] => 18/062353 [patent_app_country] => US [patent_app_date] => 2022-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4677 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18062353 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/062353
BACK GRID FOR QUANTUM DEVICE Dec 5, 2022 Pending
Array ( [id] => 20052442 [patent_doc_number] => 20250190664 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-12 [patent_title] => EVENT-DRIVEN TRACING IN STATIC TIMING ANALYSIS OF DIGITAL CIRCUIT DESIGNS [patent_app_type] => utility [patent_app_number] => 18/073100 [patent_app_country] => US [patent_app_date] => 2022-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15712 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18073100 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/073100
Event-driven tracing in static timing analysis of digital circuit designs Nov 30, 2022 Issued
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