
Brandon Bowers
Examiner (ID: 15542, Phone: (571)272-1888 , Office: P/2851 )
| Most Active Art Unit | 2851 |
| Art Unit(s) | 2825, 2851 |
| Total Applications | 903 |
| Issued Applications | 756 |
| Pending Applications | 52 |
| Abandoned Applications | 108 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 9879124
[patent_doc_number] => 08966422
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2015-02-24
[patent_title] => 'Median line based critical timing path optimization'
[patent_app_type] => utility
[patent_app_number] => 14/149150
[patent_app_country] => US
[patent_app_date] => 2014-01-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4867
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 115
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14149150
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/149150 | Median line based critical timing path optimization | Jan 6, 2014 | Issued |
Array
(
[id] => 10307864
[patent_doc_number] => 20150192866
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-07-09
[patent_title] => 'EFFICIENT OPTICAL PROXIMITY CORRECTION REPAIR FLOW METHOD AND APPARATUS'
[patent_app_type] => utility
[patent_app_number] => 14/146771
[patent_app_country] => US
[patent_app_date] => 2014-01-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4242
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14146771
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/146771 | Efficient optical proximity correction repair flow method and apparatus | Jan 2, 2014 | Issued |
Array
(
[id] => 10009746
[patent_doc_number] => 09053269
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2015-06-09
[patent_title] => 'System and methods for OPC model accuracy management and disposition'
[patent_app_type] => utility
[patent_app_number] => 14/144491
[patent_app_country] => US
[patent_app_date] => 2013-12-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 4047
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 85
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14144491
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/144491 | System and methods for OPC model accuracy management and disposition | Dec 29, 2013 | Issued |
Array
(
[id] => 9766025
[patent_doc_number] => 08850373
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-09-30
[patent_title] => 'Setting switch size and transition pattern in a resonant clock distribution system'
[patent_app_type] => utility
[patent_app_number] => 14/136770
[patent_app_country] => US
[patent_app_date] => 2013-12-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 11341
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 260
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14136770
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/136770 | Setting switch size and transition pattern in a resonant clock distribution system | Dec 19, 2013 | Issued |
Array
(
[id] => 10543754
[patent_doc_number] => 09268886
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-02-23
[patent_title] => 'Setting switch size and transition pattern in a resonant clock distribution system'
[patent_app_type] => utility
[patent_app_number] => 14/136651
[patent_app_country] => US
[patent_app_date] => 2013-12-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 11341
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 93
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14136651
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/136651 | Setting switch size and transition pattern in a resonant clock distribution system | Dec 19, 2013 | Issued |
Array
(
[id] => 10292311
[patent_doc_number] => 20150177310
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-06-25
[patent_title] => 'Testing of Semiconductor Devices and Devices, and Designs Thereof'
[patent_app_type] => utility
[patent_app_number] => 14/134847
[patent_app_country] => US
[patent_app_date] => 2013-12-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 27
[patent_figures_cnt] => 27
[patent_no_of_words] => 7631
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14134847
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/134847 | Testing of semiconductor devices and devices, and designs thereof | Dec 18, 2013 | Issued |
Array
(
[id] => 9571899
[patent_doc_number] => 20140189613
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-07-03
[patent_title] => 'VOLTAGE-RELATED ANALYSIS OF LAYOUT DESIGN DATA'
[patent_app_type] => utility
[patent_app_number] => 14/133541
[patent_app_country] => US
[patent_app_date] => 2013-12-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 12707
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14133541
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/133541 | Voltage-related analysis of layout design data | Dec 17, 2013 | Issued |
Array
(
[id] => 10895119
[patent_doc_number] => 08918750
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2014-12-23
[patent_title] => 'Multi-dimensional physical arrangement techniques using bin-packing with per-branch combination tries'
[patent_app_type] => utility
[patent_app_number] => 14/099021
[patent_app_country] => US
[patent_app_date] => 2013-12-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 12
[patent_no_of_words] => 5230
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 186
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14099021
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/099021 | Multi-dimensional physical arrangement techniques using bin-packing with per-branch combination tries | Dec 5, 2013 | Issued |
Array
(
[id] => 10059306
[patent_doc_number] => 09098668
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-08-04
[patent_title] => 'Layout of an integrated circuit'
[patent_app_type] => utility
[patent_app_number] => 14/092697
[patent_app_country] => US
[patent_app_date] => 2013-11-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 10
[patent_no_of_words] => 5712
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 205
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14092697
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/092697 | Layout of an integrated circuit | Nov 26, 2013 | Issued |
Array
(
[id] => 11687761
[patent_doc_number] => 09685813
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-06-20
[patent_title] => 'Radio communication apparatus, radio communication system, and radio communication control method'
[patent_app_type] => utility
[patent_app_number] => 14/083519
[patent_app_country] => US
[patent_app_date] => 2013-11-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 6298
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 237
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14083519
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/083519 | Radio communication apparatus, radio communication system, and radio communication control method | Nov 18, 2013 | Issued |
Array
(
[id] => 10258322
[patent_doc_number] => 20150143319
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-05-21
[patent_title] => 'DIFFERENT SCALING RATIO IN FEOL / MOL/ BEOL'
[patent_app_type] => utility
[patent_app_number] => 14/082487
[patent_app_country] => US
[patent_app_date] => 2013-11-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4578
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14082487
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/082487 | Different scaling ratio in FEOL / MOL/ BEOL | Nov 17, 2013 | Issued |
Array
(
[id] => 10258307
[patent_doc_number] => 20150143304
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-05-21
[patent_title] => 'Target Point Generation for Optical Proximity Correction'
[patent_app_type] => utility
[patent_app_number] => 14/081521
[patent_app_country] => US
[patent_app_date] => 2013-11-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3390
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14081521
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/081521 | Target point generation for optical proximity correction | Nov 14, 2013 | Issued |
Array
(
[id] => 10231001
[patent_doc_number] => 20150115994
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-04-30
[patent_title] => 'OPTIMIZATION OF INTEGRATED CIRCUIT RELIABILITY'
[patent_app_type] => utility
[patent_app_number] => 14/064337
[patent_app_country] => US
[patent_app_date] => 2013-10-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 6479
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14064337
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/064337 | Optimization of integrated circuit reliability | Oct 27, 2013 | Issued |
Array
(
[id] => 9320782
[patent_doc_number] => 20140053120
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-02-20
[patent_title] => 'ARCHITECTURAL PHYSICAL SYNTHESIS'
[patent_app_type] => utility
[patent_app_number] => 14/064067
[patent_app_country] => US
[patent_app_date] => 2013-10-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 12895
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14064067
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/064067 | Architectural physical synthesis | Oct 24, 2013 | Issued |
Array
(
[id] => 9386395
[patent_doc_number] => 20140089878
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-03-27
[patent_title] => 'DETERMINING APPARATUS, DETERMINING METHOD, AND COMPUTER PRODUCT'
[patent_app_type] => utility
[patent_app_number] => 14/031241
[patent_app_country] => US
[patent_app_date] => 2013-09-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 11100
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14031241
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/031241 | DETERMINING APPARATUS, DETERMINING METHOD, AND COMPUTER PRODUCT | Sep 18, 2013 | Abandoned |
Array
(
[id] => 9665995
[patent_doc_number] => 08813005
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2014-08-19
[patent_title] => 'Debugging using tagged flip-flops'
[patent_app_type] => utility
[patent_app_number] => 14/016941
[patent_app_country] => US
[patent_app_date] => 2013-09-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 10
[patent_no_of_words] => 5860
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 171
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14016941
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/016941 | Debugging using tagged flip-flops | Sep 2, 2013 | Issued |
Array
(
[id] => 9265003
[patent_doc_number] => 20130346932
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-12-26
[patent_title] => 'INTELLIGENT TIMING ANALYSIS AND CONSTRAINT GENERATION GUI'
[patent_app_type] => utility
[patent_app_number] => 14/010842
[patent_app_country] => US
[patent_app_date] => 2013-08-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 5941
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14010842
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/010842 | Intelligent timing analysis and constraint generation GUI | Aug 26, 2013 | Issued |
Array
(
[id] => 9695574
[patent_doc_number] => 08826205
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-09-02
[patent_title] => 'Method for verifying digital to analog converter design'
[patent_app_type] => utility
[patent_app_number] => 13/965201
[patent_app_country] => US
[patent_app_date] => 2013-08-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 3133
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 133
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13965201
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/965201 | Method for verifying digital to analog converter design | Aug 12, 2013 | Issued |
Array
(
[id] => 9866869
[patent_doc_number] => 20150046888
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-02-12
[patent_title] => 'MASK DESIGN AND DECOMPOSITION FOR SIDEWALL IMAGE TRANSFER'
[patent_app_type] => utility
[patent_app_number] => 13/960873
[patent_app_country] => US
[patent_app_date] => 2013-08-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 6008
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13960873
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/960873 | Mask design and decomposition for sidewall image transfer | Aug 6, 2013 | Issued |
Array
(
[id] => 10847883
[patent_doc_number] => 08875084
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2014-10-28
[patent_title] => 'Optimal spare latch selection for metal-only ECOs'
[patent_app_type] => utility
[patent_app_number] => 13/945191
[patent_app_country] => US
[patent_app_date] => 2013-07-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 5456
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 186
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13945191
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/945191 | Optimal spare latch selection for metal-only ECOs | Jul 17, 2013 | Issued |