Search

Brandon Bowers

Examiner (ID: 15542, Phone: (571)272-1888 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2825, 2851
Total Applications
903
Issued Applications
756
Pending Applications
52
Abandoned Applications
108

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7575586 [patent_doc_number] => 20110271242 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-03 [patent_title] => 'Efficient Redundancy Identification, Redundancy Removal, and Sequential Equivalence Checking within Designs Including Memory Arrays' [patent_app_type] => utility [patent_app_number] => 12/771677 [patent_app_country] => US [patent_app_date] => 2010-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8407 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0271/20110271242.pdf [firstpage_image] =>[orig_patent_app_number] => 12771677 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/771677
Efficient Redundancy Identification, Redundancy Removal, and Sequential Equivalence Checking within Designs Including Memory Arrays. Apr 29, 2010 Issued
Array ( [id] => 9116327 [patent_doc_number] => 08572519 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-29 [patent_title] => 'Method and apparatus for reducing implant topography reflection effect' [patent_app_type] => utility [patent_app_number] => 12/758147 [patent_app_country] => US [patent_app_date] => 2010-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 3855 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12758147 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/758147
Method and apparatus for reducing implant topography reflection effect Apr 11, 2010 Issued
Array ( [id] => 8849436 [patent_doc_number] => 08458636 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-06-04 [patent_title] => 'Filling vacant areas of an integrated circuit design' [patent_app_type] => utility [patent_app_number] => 12/727227 [patent_app_country] => US [patent_app_date] => 2010-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 9318 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12727227 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/727227
Filling vacant areas of an integrated circuit design Mar 17, 2010 Issued
Array ( [id] => 8837307 [patent_doc_number] => 08453076 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-05-28 [patent_title] => 'Wavefront engineering of mask data for semiconductor device design' [patent_app_type] => utility [patent_app_number] => 12/725287 [patent_app_country] => US [patent_app_date] => 2010-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 8272 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12725287 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/725287
Wavefront engineering of mask data for semiconductor device design Mar 15, 2010 Issued
Array ( [id] => 8412691 [patent_doc_number] => 08276102 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-09-25 [patent_title] => 'Spatial correlation-based estimation of yield of integrated circuits' [patent_app_type] => utility [patent_app_number] => 12/718567 [patent_app_country] => US [patent_app_date] => 2010-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 23 [patent_no_of_words] => 10508 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12718567 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/718567
Spatial correlation-based estimation of yield of integrated circuits Mar 4, 2010 Issued
Array ( [id] => 6652455 [patent_doc_number] => 20100229144 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-09 [patent_title] => 'SYSTEM AND METHOD FOR BEHAVIORAL SYNTHESIS' [patent_app_type] => utility [patent_app_number] => 12/717377 [patent_app_country] => US [patent_app_date] => 2010-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 5505 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0229/20100229144.pdf [firstpage_image] =>[orig_patent_app_number] => 12717377 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/717377
SYSTEM AND METHOD FOR BEHAVIORAL SYNTHESIS Mar 3, 2010 Abandoned
Array ( [id] => 8461013 [patent_doc_number] => 08296699 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-10-23 [patent_title] => 'Method and system for supporting both analog and digital signal traffic on a single hierarchical connection for mixed-signal verification' [patent_app_type] => utility [patent_app_number] => 12/714027 [patent_app_country] => US [patent_app_date] => 2010-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 7576 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12714027 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/714027
Method and system for supporting both analog and digital signal traffic on a single hierarchical connection for mixed-signal verification Feb 25, 2010 Issued
Array ( [id] => 7728942 [patent_doc_number] => 20120013373 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-01-19 [patent_title] => 'SEMICONDUCTOR DEVICE, CIRCUIT CORRECTION METHOD, DESIGN SUPPORT DEVICE, AND RECORDING MEDIUM STORING DESIGN SUPPORT PROGRAM' [patent_app_type] => utility [patent_app_number] => 13/203197 [patent_app_country] => US [patent_app_date] => 2010-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9785 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0013/20120013373.pdf [firstpage_image] =>[orig_patent_app_number] => 13203197 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/203197
SEMICONDUCTOR DEVICE, CIRCUIT CORRECTION METHOD, DESIGN SUPPORT DEVICE, AND RECORDING MEDIUM STORING DESIGN SUPPORT PROGRAM Feb 8, 2010 Abandoned
Array ( [id] => 6074271 [patent_doc_number] => 20110047524 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-02-24 [patent_title] => 'SYSTEM AND METHOD FOR INSPECTING LAYOUT OF A PRINTED CIRCUIT BOARD' [patent_app_type] => utility [patent_app_number] => 12/701677 [patent_app_country] => US [patent_app_date] => 2010-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2027 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0047/20110047524.pdf [firstpage_image] =>[orig_patent_app_number] => 12701677 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/701677
System and method for inspecting layout of a printed circuit board Feb 7, 2010 Issued
Array ( [id] => 8959178 [patent_doc_number] => 08504972 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-06 [patent_title] => 'Standard cells having flexible layout architecture/boundaries' [patent_app_type] => utility [patent_app_number] => 12/697887 [patent_app_country] => US [patent_app_date] => 2010-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3668 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12697887 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/697887
Standard cells having flexible layout architecture/boundaries Jan 31, 2010 Issued
Array ( [id] => 8389160 [patent_doc_number] => 08266570 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-09-11 [patent_title] => 'Density-based area recovery in electronic design automation' [patent_app_type] => utility [patent_app_number] => 12/697077 [patent_app_country] => US [patent_app_date] => 2010-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8578 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12697077 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/697077
Density-based area recovery in electronic design automation Jan 28, 2010 Issued
Array ( [id] => 8552404 [patent_doc_number] => 08327303 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-12-04 [patent_title] => 'Template-based real number behavioral modeling' [patent_app_type] => utility [patent_app_number] => 12/692497 [patent_app_country] => US [patent_app_date] => 2010-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5016 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12692497 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/692497
Template-based real number behavioral modeling Jan 21, 2010 Issued
Array ( [id] => 7780220 [patent_doc_number] => 08122389 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-02-21 [patent_title] => 'Apparatus and method for segmenting edges for optical proximity correction' [patent_app_type] => utility [patent_app_number] => 12/690791 [patent_app_country] => US [patent_app_date] => 2010-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 7605 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/122/08122389.pdf [firstpage_image] =>[orig_patent_app_number] => 12690791 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/690791
Apparatus and method for segmenting edges for optical proximity correction Jan 19, 2010 Issued
Array ( [id] => 6191302 [patent_doc_number] => 20110173586 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-07-14 [patent_title] => 'METHOD FOR CREATING ELECTRICALLY TESTABLE PATTERNS' [patent_app_type] => utility [patent_app_number] => 12/687147 [patent_app_country] => US [patent_app_date] => 2010-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 6153 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0173/20110173586.pdf [firstpage_image] =>[orig_patent_app_number] => 12687147 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/687147
Method for creating electrically testable patterns Jan 13, 2010 Issued
Array ( [id] => 6241439 [patent_doc_number] => 20100269085 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-21 [patent_title] => 'Automated Generation of Oxide Pillar Slot Shapes in Silicon-On-Insulator Formation Technology' [patent_app_type] => utility [patent_app_number] => 12/621564 [patent_app_country] => US [patent_app_date] => 2009-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 2484 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0269/20100269085.pdf [firstpage_image] =>[orig_patent_app_number] => 12621564 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/621564
Automated generation of oxide pillar slot shapes in silicon-on-insulator formation technology Nov 18, 2009 Issued
Array ( [id] => 9579034 [patent_doc_number] => 08769471 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-07-01 [patent_title] => 'Producing electrical circuit patterns using multi-population transformation' [patent_app_type] => utility [patent_app_number] => 13/061344 [patent_app_country] => US [patent_app_date] => 2009-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3638 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13061344 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/061344
Producing electrical circuit patterns using multi-population transformation Oct 25, 2009 Issued
Array ( [id] => 6383933 [patent_doc_number] => 20100077178 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-25 [patent_title] => 'Method and apparatus for extending processing time in one pipeline stage' [patent_app_type] => utility [patent_app_number] => 12/583393 [patent_app_country] => US [patent_app_date] => 2009-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 57 [patent_figures_cnt] => 57 [patent_no_of_words] => 37514 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0077/20100077178.pdf [firstpage_image] =>[orig_patent_app_number] => 12583393 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/583393
Method and apparatus for extending processing time in one pipeline stage Aug 19, 2009 Abandoned
Array ( [id] => 4582572 [patent_doc_number] => 07840928 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-11-23 [patent_title] => 'Circuit design tools with optimization assistance' [patent_app_type] => utility [patent_app_number] => 12/483216 [patent_app_country] => US [patent_app_date] => 2009-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 11013 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/840/07840928.pdf [firstpage_image] =>[orig_patent_app_number] => 12483216 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/483216
Circuit design tools with optimization assistance Jun 10, 2009 Issued
Array ( [id] => 9029809 [patent_doc_number] => 08539407 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-09-17 [patent_title] => 'Intelligent timing analysis and constraint generation GUI' [patent_app_type] => utility [patent_app_number] => 12/388741 [patent_app_country] => US [patent_app_date] => 2009-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 5912 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12388741 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/388741
Intelligent timing analysis and constraint generation GUI Feb 18, 2009 Issued
Array ( [id] => 5548358 [patent_doc_number] => 20090158235 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-18 [patent_title] => 'SYNTHESIS OF ELECTRONIC CIRCUITS' [patent_app_type] => utility [patent_app_number] => 12/351507 [patent_app_country] => US [patent_app_date] => 2009-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4247 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0158/20090158235.pdf [firstpage_image] =>[orig_patent_app_number] => 12351507 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/351507
Synthesis of electronic circuits Jan 8, 2009 Issued
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