Brandon Bowers

Array ( [id] => 5535435 [patent_doc_number] => 20090235223 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-09-17 [patent_title] => 'PROGRAM GENERATION APPARATUS AND PROGRAM GENERATION METHOD' [patent_app_type] => utility [patent_app_number] => 12/350597 [patent_app_country] => US [patent_app_date] => 2009-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7264 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0235/20090235223.pdf [firstpage_image] =>[orig_patent_app_number] => 12350597 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7686590 [patent_doc_number] => 20090177701 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-09 [patent_title] => 'Method to Avoid Malconnections with Respect to Voltage Levels of Electronic Components of Circuit Boards During Circuit Board Design' [patent_app_type] => utility [patent_app_number] => 12/348387 [patent_app_country] => US [patent_app_date] => 2009-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3295 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0177/20090177701.pdf [firstpage_image] =>[orig_patent_app_number] => 12348387 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8087781 [patent_doc_number] => 08151224 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-04-03 [patent_title] => 'Method of designing integrated circuits including providing an option to select a mask layer set' [patent_app_type] => utility [patent_app_number] => 12/345187 [patent_app_country] => US [patent_app_date] => 2008-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 4461 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/151/08151224.pdf [firstpage_image] =>[orig_patent_app_number] => 12345187 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8678838 [patent_doc_number] => 08386975 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-02-26 [patent_title] => 'Method, system, and computer program product for improved electrical analysis' [patent_app_type] => utility [patent_app_number] => 12/344327 [patent_app_country] => US [patent_app_date] => 2008-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 38 [patent_no_of_words] => 7074 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12344327 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8319815 [patent_doc_number] => 08234609 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-31 [patent_title] => 'Method and system for implementing top down design and verification of an electronic design' [patent_app_type] => utility [patent_app_number] => 12/340677 [patent_app_country] => US [patent_app_date] => 2008-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9395 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12340677 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8438322 [patent_doc_number] => 08286107 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-09 [patent_title] => 'Methods and systems for process compensation technique acceleration' [patent_app_type] => utility [patent_app_number] => 12/340406 [patent_app_country] => US [patent_app_date] => 2008-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 6937 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12340406 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5548356 [patent_doc_number] => 20090158233 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-18 [patent_title] => 'Automatic design method and computer program thereof' [patent_app_type] => utility [patent_app_number] => 12/314917 [patent_app_country] => US [patent_app_date] => 2008-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 6568 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0158/20090158233.pdf [firstpage_image] =>[orig_patent_app_number] => 12314917 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5442932 [patent_doc_number] => 20090094571 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-09 [patent_title] => 'Method and system for outputting a sequence of commands and data described by a flowchart' [patent_app_type] => utility [patent_app_number] => 12/315998 [patent_app_country] => US [patent_app_date] => 2008-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4617 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0094/20090094571.pdf [firstpage_image] =>[orig_patent_app_number] => 12315998 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5424389 [patent_doc_number] => 20090150845 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-11 [patent_title] => 'METHOD FOR DRIVING CURRENT OF CELL LIBRARY' [patent_app_type] => utility [patent_app_number] => 12/326897 [patent_app_country] => US [patent_app_date] => 2008-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2086 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0150/20090150845.pdf [firstpage_image] =>[orig_patent_app_number] => 12326897 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7756702 [patent_doc_number] => 08112731 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-02-07 [patent_title] => 'Congestion-driven placement systems and methods for programmable logic devices' [patent_app_type] => utility [patent_app_number] => 12/277217 [patent_app_country] => US [patent_app_date] => 2008-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 7407 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/112/08112731.pdf [firstpage_image] =>[orig_patent_app_number] => 12277217 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8627057 [patent_doc_number] => 08359561 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-01-22 [patent_title] => 'Equivalence verification between transaction level models and RTL at the example to processors' [patent_app_type] => utility [patent_app_number] => 12/275557 [patent_app_country] => US [patent_app_date] => 2008-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 28744 [patent_no_of_claims] => 52 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12275557 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8235667 [patent_doc_number] => 08201127 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-06-12 [patent_title] => 'Method and apparatus for reducing clock signal power consumption within an integrated circuit' [patent_app_type] => utility [patent_app_number] => 12/273407 [patent_app_country] => US [patent_app_date] => 2008-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5868 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/201/08201127.pdf [firstpage_image] =>[orig_patent_app_number] => 12273407 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7683910 [patent_doc_number] => 20100122231 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-13 [patent_title] => 'ELECTRICALLY-DRIVEN OPTICAL PROXIMITY CORRECTION TO COMPENSATE FOR NON-OPTICAL EFFECTS' [patent_app_type] => utility [patent_app_number] => 12/269477 [patent_app_country] => US [patent_app_date] => 2008-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5851 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0122/20100122231.pdf [firstpage_image] =>[orig_patent_app_number] => 12269477 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8472853 [patent_doc_number] => 08302046 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-10-30 [patent_title] => 'Compact modeling of circuit stages for static timing analysis of integrated circuit designs' [patent_app_type] => utility [patent_app_number] => 12/269037 [patent_app_country] => US [patent_app_date] => 2008-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 41 [patent_no_of_words] => 15741 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12269037 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5266946 [patent_doc_number] => 20090119631 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-07 [patent_title] => 'Variability-Aware Asynchronous Scheme for High-Performance Delay Matching' [patent_app_type] => utility [patent_app_number] => 12/265657 [patent_app_country] => US [patent_app_date] => 2008-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 34 [patent_no_of_words] => 22583 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0119/20090119631.pdf [firstpage_image] =>[orig_patent_app_number] => 12265657 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 47955 [patent_doc_number] => 07784002 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-24 [patent_title] => 'Systems for using relative positioning in structures with dynamic ranges' [patent_app_type] => utility [patent_app_number] => 12/253481 [patent_app_country] => US [patent_app_date] => 2008-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 6988 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 395 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/784/07784002.pdf [firstpage_image] =>[orig_patent_app_number] => 12253481 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5516915 [patent_doc_number] => 20090217222 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-27 [patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/211842 [patent_app_country] => US [patent_app_date] => 2008-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 6038 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0217/20090217222.pdf [firstpage_image] =>[orig_patent_app_number] => 12211842 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6313174 [patent_doc_number] => 20100070942 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-18 [patent_title] => 'Automated Metal Pattern Generation for Integrated Circuits' [patent_app_type] => utility [patent_app_number] => 12/210212 [patent_app_country] => US [patent_app_date] => 2008-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 22567 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0070/20100070942.pdf [firstpage_image] =>[orig_patent_app_number] => 12210212 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5273751 [patent_doc_number] => 20090077527 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-19 [patent_title] => 'System for Determining Repetitive Work Units' [patent_app_type] => utility [patent_app_number] => 12/207962 [patent_app_country] => US [patent_app_date] => 2008-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9981 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0077/20090077527.pdf [firstpage_image] =>[orig_patent_app_number] => 12207962 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5438022 [patent_doc_number] => 20090172609 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-02 [patent_title] => 'JITTER AMOUNT ESTIMATING METHOD, METHOD FOR CALCULATING CORRELATION BETWEEN AMOUNT OF SIMULTANEOUSLY OPERATING SIGNAL NOISE AND JITTER AMOUNT, AND RECORDING MEDIUM' [patent_app_type] => utility [patent_app_number] => 12/201732 [patent_app_country] => US [patent_app_date] => 2008-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 10943 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0172/20090172609.pdf [firstpage_image] =>[orig_patent_app_number] => 12201732 [rel_patent_id] =>[rel_patent_doc_number] =>)