Search

Brandon Bowers

Examiner (ID: 15542, Phone: (571)272-1888 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2825, 2851
Total Applications
903
Issued Applications
756
Pending Applications
52
Abandoned Applications
108

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7495217 [patent_doc_number] => 08032854 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-10-04 [patent_title] => '3-stack floorplan for floating point unit' [patent_app_type] => utility [patent_app_number] => 12/201092 [patent_app_country] => US [patent_app_date] => 2008-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3565 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/032/08032854.pdf [firstpage_image] =>[orig_patent_app_number] => 12201092 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/201092
3-stack floorplan for floating point unit Aug 28, 2008 Issued
Array ( [id] => 4508910 [patent_doc_number] => 07958464 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-06-07 [patent_title] => 'Electron beam patterning' [patent_app_type] => utility [patent_app_number] => 12/199922 [patent_app_country] => US [patent_app_date] => 2008-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3534 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/958/07958464.pdf [firstpage_image] =>[orig_patent_app_number] => 12199922 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/199922
Electron beam patterning Aug 27, 2008 Issued
Array ( [id] => 4626895 [patent_doc_number] => 08006207 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-23 [patent_title] => 'Parallel intrusion search in hierarchical VLSI designs with substituting scan line' [patent_app_type] => utility [patent_app_number] => 12/198172 [patent_app_country] => US [patent_app_date] => 2008-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 9795 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/006/08006207.pdf [firstpage_image] =>[orig_patent_app_number] => 12198172 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/198172
Parallel intrusion search in hierarchical VLSI designs with substituting scan line Aug 25, 2008 Issued
Array ( [id] => 5273732 [patent_doc_number] => 20090077508 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-19 [patent_title] => 'ACCELERATED LIFE TESTING OF SEMICONDUCTOR CHIPS' [patent_app_type] => utility [patent_app_number] => 12/193752 [patent_app_country] => US [patent_app_date] => 2008-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 17833 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0077/20090077508.pdf [firstpage_image] =>[orig_patent_app_number] => 12193752 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/193752
ACCELERATED LIFE TESTING OF SEMICONDUCTOR CHIPS Aug 18, 2008 Abandoned
Array ( [id] => 8011117 [patent_doc_number] => 08086977 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-12-27 [patent_title] => 'Design Structure for switching digital circuit clock net driver without losing clock pulses' [patent_app_type] => utility [patent_app_number] => 12/192272 [patent_app_country] => US [patent_app_date] => 2008-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5545 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/086/08086977.pdf [firstpage_image] =>[orig_patent_app_number] => 12192272 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/192272
Design Structure for switching digital circuit clock net driver without losing clock pulses Aug 14, 2008 Issued
Array ( [id] => 8343219 [patent_doc_number] => 08245161 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-08-14 [patent_title] => 'Verification of computer simulation of photolithographic process' [patent_app_type] => utility [patent_app_number] => 12/190017 [patent_app_country] => US [patent_app_date] => 2008-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5195 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12190017 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/190017
Verification of computer simulation of photolithographic process Aug 11, 2008 Issued
Array ( [id] => 7557513 [patent_doc_number] => 08069423 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-29 [patent_title] => 'System and method for model based multi-patterning optimization' [patent_app_type] => utility [patent_app_number] => 12/189692 [patent_app_country] => US [patent_app_date] => 2008-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 26 [patent_no_of_words] => 9781 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/069/08069423.pdf [firstpage_image] =>[orig_patent_app_number] => 12189692 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/189692
System and method for model based multi-patterning optimization Aug 10, 2008 Issued
Array ( [id] => 5523296 [patent_doc_number] => 20090031277 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-29 [patent_title] => 'ARCHITECTURAL PHYSICAL SYNTHESIS' [patent_app_type] => utility [patent_app_number] => 12/177867 [patent_app_country] => US [patent_app_date] => 2008-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 12896 [patent_no_of_claims] => 99 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0031/20090031277.pdf [firstpage_image] =>[orig_patent_app_number] => 12177867 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/177867
Architectural physical synthesis Jul 21, 2008 Issued
Array ( [id] => 5523296 [patent_doc_number] => 20090031277 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-29 [patent_title] => 'ARCHITECTURAL PHYSICAL SYNTHESIS' [patent_app_type] => utility [patent_app_number] => 12/177867 [patent_app_country] => US [patent_app_date] => 2008-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 12896 [patent_no_of_claims] => 99 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0031/20090031277.pdf [firstpage_image] =>[orig_patent_app_number] => 12177867 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/177867
Architectural physical synthesis Jul 21, 2008 Issued
Array ( [id] => 5523296 [patent_doc_number] => 20090031277 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-29 [patent_title] => 'ARCHITECTURAL PHYSICAL SYNTHESIS' [patent_app_type] => utility [patent_app_number] => 12/177867 [patent_app_country] => US [patent_app_date] => 2008-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 12896 [patent_no_of_claims] => 99 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0031/20090031277.pdf [firstpage_image] =>[orig_patent_app_number] => 12177867 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/177867
Architectural physical synthesis Jul 21, 2008 Issued
Array ( [id] => 5523296 [patent_doc_number] => 20090031277 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-29 [patent_title] => 'ARCHITECTURAL PHYSICAL SYNTHESIS' [patent_app_type] => utility [patent_app_number] => 12/177867 [patent_app_country] => US [patent_app_date] => 2008-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 12896 [patent_no_of_claims] => 99 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0031/20090031277.pdf [firstpage_image] =>[orig_patent_app_number] => 12177867 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/177867
Architectural physical synthesis Jul 21, 2008 Issued
Array ( [id] => 4961780 [patent_doc_number] => 20080276205 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-06 [patent_title] => 'COMPUTER PROGRAM PRODUCT FOR DESIGNING MEMORY CIRCUITS HAVING SINGLE-ENDED MEMORY CELLS WITH IMPROVED READ STABILITY' [patent_app_type] => utility [patent_app_number] => 12/174707 [patent_app_country] => US [patent_app_date] => 2008-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4678 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0276/20080276205.pdf [firstpage_image] =>[orig_patent_app_number] => 12174707 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/174707
Computer program product for designing memory circuits having single-ended memory cells with improved read stability Jul 16, 2008 Issued
Array ( [id] => 5292248 [patent_doc_number] => 20090024978 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-22 [patent_title] => 'SEMICONDUCTOR DEVICE MASK, METHOD OF FORMING THE SAME AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/169577 [patent_app_country] => US [patent_app_date] => 2008-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2865 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0024/20090024978.pdf [firstpage_image] =>[orig_patent_app_number] => 12169577 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/169577
SEMICONDUCTOR DEVICE MASK, METHOD OF FORMING THE SAME AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME Jul 7, 2008 Abandoned
Array ( [id] => 5264659 [patent_doc_number] => 20090117344 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-07 [patent_title] => 'METHOD OF CORRECTING MASK PATTERN, PHOTO MASK, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/167497 [patent_app_country] => US [patent_app_date] => 2008-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7027 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0117/20090117344.pdf [firstpage_image] =>[orig_patent_app_number] => 12167497 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/167497
METHOD OF CORRECTING MASK PATTERN, PHOTO MASK, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE Jul 2, 2008 Abandoned
Array ( [id] => 4499657 [patent_doc_number] => 07886256 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-02-08 [patent_title] => 'Timing analysis of a mapped logic design using physical delays' [patent_app_type] => utility [patent_app_number] => 12/146507 [patent_app_country] => US [patent_app_date] => 2008-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 6303 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/886/07886256.pdf [firstpage_image] =>[orig_patent_app_number] => 12146507 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/146507
Timing analysis of a mapped logic design using physical delays Jun 25, 2008 Issued
Array ( [id] => 4710193 [patent_doc_number] => 20080298719 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-04 [patent_title] => 'SUB-RESOLUTION ALIGNMENT OF IMAGES' [patent_app_type] => utility [patent_app_number] => 12/144495 [patent_app_country] => US [patent_app_date] => 2008-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6685 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0298/20080298719.pdf [firstpage_image] =>[orig_patent_app_number] => 12144495 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/144495
SUB-RESOLUTION ALIGNMENT OF IMAGES Jun 22, 2008 Abandoned
Array ( [id] => 4780685 [patent_doc_number] => 20080288684 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-20 [patent_title] => 'DESIGN STRUCTURE FOR AN ADDRESS TRANSLATION DEVICE' [patent_app_type] => utility [patent_app_number] => 12/144417 [patent_app_country] => US [patent_app_date] => 2008-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7691 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0288/20080288684.pdf [firstpage_image] =>[orig_patent_app_number] => 12144417 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/144417
DESIGN STRUCTURE FOR AN ADDRESS TRANSLATION DEVICE Jun 22, 2008 Abandoned
Array ( [id] => 5399906 [patent_doc_number] => 20090319969 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-24 [patent_title] => 'METHOD AND SYSTEM FOR PERFORMING STATISTICAL LEAKAGE CHARACTERIZATION, ANALYSIS, AND MODELING' [patent_app_type] => utility [patent_app_number] => 12/143547 [patent_app_country] => US [patent_app_date] => 2008-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3465 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0319/20090319969.pdf [firstpage_image] =>[orig_patent_app_number] => 12143547 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/143547
Method and system for performing statistical leakage characterization, analysis, and modeling Jun 19, 2008 Issued
Array ( [id] => 4761361 [patent_doc_number] => 20080313587 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-18 [patent_title] => 'Apparatus and method for performing a sequence of verification tests to verify a design of a data processing system' [patent_app_type] => utility [patent_app_number] => 12/155337 [patent_app_country] => US [patent_app_date] => 2008-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8609 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0313/20080313587.pdf [firstpage_image] =>[orig_patent_app_number] => 12155337 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/155337
Apparatus and method for performing a sequence of verification tests to verify a design of a data processing system Jun 2, 2008 Issued
Array ( [id] => 8645792 [patent_doc_number] => 08370791 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-02-05 [patent_title] => 'System and method for performing next placements and pruning of disallowed placements for programming an integrated circuit' [patent_app_type] => utility [patent_app_number] => 12/132527 [patent_app_country] => US [patent_app_date] => 2008-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5320 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12132527 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/132527
System and method for performing next placements and pruning of disallowed placements for programming an integrated circuit Jun 2, 2008 Issued
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