Search

Brandon Bowers

Examiner (ID: 3343)

Most Active Art Unit
2851
Art Unit(s)
2825, 2851
Total Applications
898
Issued Applications
755
Pending Applications
50
Abandoned Applications
108

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19363147 [patent_doc_number] => 20240265181 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-08 [patent_title] => OPTIMIZATION METHOD FOR DIGITAL INTEGRATED CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/571727 [patent_app_country] => US [patent_app_date] => 2023-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4931 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 496 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18571727 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/571727
Optimization method for digital integrated circuit Jan 2, 2023 Issued
Array ( [id] => 18471670 [patent_doc_number] => 20230205956 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-29 [patent_title] => NEURAL NETWORK WITH ON-THE-FLY GENERATION OF THE NETWORK PARAMETERS [patent_app_type] => utility [patent_app_number] => 18/145236 [patent_app_country] => US [patent_app_date] => 2022-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10322 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18145236 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/145236
NEURAL NETWORK WITH ON-THE-FLY GENERATION OF THE NETWORK PARAMETERS Dec 21, 2022 Pending
Array ( [id] => 18454886 [patent_doc_number] => 20230196167 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-22 [patent_title] => BACK GRID FOR QUANTUM DEVICE [patent_app_type] => utility [patent_app_number] => 18/062353 [patent_app_country] => US [patent_app_date] => 2022-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4677 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18062353 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/062353
BACK GRID FOR QUANTUM DEVICE Dec 5, 2022 Pending
Array ( [id] => 20052442 [patent_doc_number] => 20250190664 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-12 [patent_title] => EVENT-DRIVEN TRACING IN STATIC TIMING ANALYSIS OF DIGITAL CIRCUIT DESIGNS [patent_app_type] => utility [patent_app_number] => 18/073100 [patent_app_country] => US [patent_app_date] => 2022-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15712 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18073100 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/073100
Event-driven tracing in static timing analysis of digital circuit designs Nov 30, 2022 Issued
Array ( [id] => 18471686 [patent_doc_number] => 20230205972 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-29 [patent_title] => COMPUTING AND DISPLAYING A PREDICTED OVERLAP SHAPE IN AN IC DESIGN BASED ON PREDICTED MISALIGNMENT OF METAL LAYERS [patent_app_type] => utility [patent_app_number] => 17/992899 [patent_app_country] => US [patent_app_date] => 2022-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12477 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17992899 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/992899
Computing and displaying a predicted overlap shape in an IC design based on predicted misalignment of metal layers Nov 21, 2022 Issued
Array ( [id] => 18407308 [patent_doc_number] => 20230168660 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-01 [patent_title] => BASED ON MULTIPLE MANUFACTURING PROCESS VARIATIONS, PRODUCING MULTIPLE CONTOURS REPRESENTING PREDICTED SHAPES OF AN IC DESIGN COMPONENT [patent_app_type] => utility [patent_app_number] => 17/992870 [patent_app_country] => US [patent_app_date] => 2022-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 23497 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17992870 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/992870
BASED ON MULTIPLE MANUFACTURING PROCESS VARIATIONS, PRODUCING MULTIPLE CONTOURS REPRESENTING PREDICTED SHAPES OF AN IC DESIGN COMPONENT Nov 21, 2022 Pending
Array ( [id] => 20611031 [patent_doc_number] => 12586636 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-24 [patent_title] => Analog-digital hybrid computing method and neuromorphic system using the same [patent_app_type] => utility [patent_app_number] => 17/989964 [patent_app_country] => US [patent_app_date] => 2022-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 5979 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 296 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17989964 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/989964
Analog-digital hybrid computing method and neuromorphic system using the same Nov 17, 2022 Issued
Array ( [id] => 18222516 [patent_doc_number] => 20230061510 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => LAYOUT AND PHOTOMASK [patent_app_type] => utility [patent_app_number] => 17/982530 [patent_app_country] => US [patent_app_date] => 2022-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5978 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17982530 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/982530
LAYOUT AND PHOTOMASK Nov 7, 2022 Pending
Array ( [id] => 18569353 [patent_doc_number] => 20230259689 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-17 [patent_title] => AUTOMATED TRANSISTOR-LEVEL PLACEMENT FOR DESIGN OF INTEGRATED CIRCUITS [patent_app_type] => utility [patent_app_number] => 17/957621 [patent_app_country] => US [patent_app_date] => 2022-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6873 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17957621 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/957621
Automated transistor-level placement for design of integrated circuits Sep 29, 2022 Issued
Array ( [id] => 18295991 [patent_doc_number] => 20230105677 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-06 [patent_title] => SYNTHESIS OF A NETWORK-ON-CHIP (NoC) FOR INSERTION OF PIPELINE STAGES [patent_app_type] => utility [patent_app_number] => 17/949193 [patent_app_country] => US [patent_app_date] => 2022-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4671 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17949193 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/949193
Synthesis of a network-on-chip (NoC) for insertion of pipeline stages Sep 19, 2022 Issued
Array ( [id] => 18613663 [patent_doc_number] => 20230280399 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-07 [patent_title] => SYSTEM AND METHOD TO WEIGHT DEFECTS WITH CO-LOCATED MODELED FAULTS [patent_app_type] => utility [patent_app_number] => 17/889491 [patent_app_country] => US [patent_app_date] => 2022-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11536 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -30 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17889491 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/889491
System and method to weight defects with co-located modeled faults Aug 16, 2022 Issued
Array ( [id] => 19313430 [patent_doc_number] => 12039245 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-16 [patent_title] => Semiconductor device including standard cell having split portions [patent_app_type] => utility [patent_app_number] => 17/818208 [patent_app_country] => US [patent_app_date] => 2022-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 13740 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17818208 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/818208
Semiconductor device including standard cell having split portions Aug 7, 2022 Issued
Array ( [id] => 20331807 [patent_doc_number] => 12462084 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-04 [patent_title] => Power envelope analysis for the thermal optimization of multi-chip modules [patent_app_type] => utility [patent_app_number] => 17/815732 [patent_app_country] => US [patent_app_date] => 2022-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 23 [patent_no_of_words] => 1491 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17815732 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/815732
Power envelope analysis for the thermal optimization of multi-chip modules Jul 27, 2022 Issued
Array ( [id] => 18009375 [patent_doc_number] => 20220368142 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-17 [patent_title] => POWER SAVING CIRCUIT FOR EMBEDDED BATTERY APPLICATIONS [patent_app_type] => utility [patent_app_number] => 17/875686 [patent_app_country] => US [patent_app_date] => 2022-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9825 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17875686 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/875686
POWER SAVING CIRCUIT FOR EMBEDDED BATTERY APPLICATIONS Jul 27, 2022 Abandoned
Array ( [id] => 18194144 [patent_doc_number] => 20230047663 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-16 [patent_title] => METASURFACES FOR HIGH EFFICIENCY WIRELESS POWER TRANSFER SYSTEMS [patent_app_type] => utility [patent_app_number] => 17/871567 [patent_app_country] => US [patent_app_date] => 2022-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11467 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17871567 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/871567
METASURFACES FOR HIGH EFFICIENCY WIRELESS POWER TRANSFER SYSTEMS Jul 21, 2022 Pending
Array ( [id] => 17983903 [patent_doc_number] => 20220349939 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-03 [patent_title] => INJECTION DEVICE, SEMICONDUCTOR TESTING SYSTEM AND ITS TESTING METHOD [patent_app_type] => utility [patent_app_number] => 17/863681 [patent_app_country] => US [patent_app_date] => 2022-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3900 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 270 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17863681 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/863681
Injection device, semiconductor testing system and its testing method Jul 12, 2022 Issued
Array ( [id] => 18905078 [patent_doc_number] => 20240020563 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-18 [patent_title] => QUANTUM CIRCUIT FOR TRANSFORMATION OF MIXED STATE VECTORS [patent_app_type] => utility [patent_app_number] => 17/863449 [patent_app_country] => US [patent_app_date] => 2022-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12416 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17863449 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/863449
Quantum circuit for transformation of mixed state vectors Jul 12, 2022 Issued
Array ( [id] => 17948171 [patent_doc_number] => 20220335190 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-20 [patent_title] => DYNAMIC POWER LOAD LINE BY CONFIGURATION [patent_app_type] => utility [patent_app_number] => 17/856776 [patent_app_country] => US [patent_app_date] => 2022-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5811 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17856776 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/856776
DYNAMIC POWER LOAD LINE BY CONFIGURATION Jun 30, 2022 Pending
Array ( [id] => 18110922 [patent_doc_number] => 20230003802 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-05 [patent_title] => LEBESGUE SAMPLING-BASED LITHIUM-ION BATTERY STATE-OF-CHARGE DIAGNOSIS AND PROGNOSIS [patent_app_type] => utility [patent_app_number] => 17/854980 [patent_app_country] => US [patent_app_date] => 2022-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3162 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17854980 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/854980
Lebesgue sampling-based lithium-ion battery state-of-charge diagnosis and prognosis Jun 29, 2022 Issued
Array ( [id] => 18695224 [patent_doc_number] => 20230325645 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-12 [patent_title] => ARTIFICIAL NEURAL NETWORK COMPRISING A THREE-DIMENSIONAL INTEGRATED CIRCUIT [patent_app_type] => utility [patent_app_number] => 17/848371 [patent_app_country] => US [patent_app_date] => 2022-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17501 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -45 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17848371 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/848371
ARTIFICIAL NEURAL NETWORK COMPRISING A THREE-DIMENSIONAL INTEGRATED CIRCUIT Jun 22, 2022 Pending
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