Search

Brandon Bowers

Examiner (ID: 15542, Phone: (571)272-1888 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2825, 2851
Total Applications
903
Issued Applications
756
Pending Applications
52
Abandoned Applications
108

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4447711 [patent_doc_number] => 07930667 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-04-19 [patent_title] => 'System and method of automated wire and via layout optimization description' [patent_app_type] => utility [patent_app_number] => 11/465473 [patent_app_country] => US [patent_app_date] => 2006-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 3981 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/930/07930667.pdf [firstpage_image] =>[orig_patent_app_number] => 11465473 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/465473
System and method of automated wire and via layout optimization description Aug 17, 2006 Issued
Array ( [id] => 4671787 [patent_doc_number] => 20080046848 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-21 [patent_title] => 'METHOD AND COMPUTER PROGRAM FOR STATIC TIMING ANALYSIS WITH DELAY DE-RATING AND CLOCK CONSERVATISM REDUCTION' [patent_app_type] => utility [patent_app_number] => 11/465662 [patent_app_country] => US [patent_app_date] => 2006-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5278 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0046/20080046848.pdf [firstpage_image] =>[orig_patent_app_number] => 11465662 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/465662
Method and computer program for static timing analysis with delay de-rating and clock conservatism reduction Aug 17, 2006 Issued
Array ( [id] => 4659485 [patent_doc_number] => 20080028347 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-31 [patent_title] => 'Transformation of IC designs for formal verification' [patent_app_type] => utility [patent_app_number] => 11/495136 [patent_app_country] => US [patent_app_date] => 2006-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 22676 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0028/20080028347.pdf [firstpage_image] =>[orig_patent_app_number] => 11495136 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/495136
Transformation of IC designs for formal verification Jul 27, 2006 Issued
Array ( [id] => 5206715 [patent_doc_number] => 20070028197 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-01 [patent_title] => 'METHOD AND APPARATUS FOR AUTO-GENERATION OF SHIFT REGISTER FILE FOR HIGH-LEVEL SYNTHESIS COMPILER' [patent_app_type] => utility [patent_app_number] => 11/460396 [patent_app_country] => US [patent_app_date] => 2006-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5948 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0028/20070028197.pdf [firstpage_image] =>[orig_patent_app_number] => 11460396 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/460396
METHOD AND APPARATUS FOR AUTO-GENERATION OF SHIFT REGISTER FILE FOR HIGH-LEVEL SYNTHESIS COMPILER Jul 26, 2006 Abandoned
Array ( [id] => 5161763 [patent_doc_number] => 20070174807 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-26 [patent_title] => 'Semiconductor device manufacturing method, library used for the same, recording medium, and semiconductor device manufacturing system' [patent_app_type] => utility [patent_app_number] => 11/487970 [patent_app_country] => US [patent_app_date] => 2006-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5796 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0174/20070174807.pdf [firstpage_image] =>[orig_patent_app_number] => 11487970 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/487970
Semiconductor device manufacturing method, library used for the same, recording medium, and semiconductor device manufacturing system Jul 17, 2006 Abandoned
Array ( [id] => 10873388 [patent_doc_number] => 08898609 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-11-25 [patent_title] => 'Method and apparatus for integrating signal transition time modeling during routing' [patent_app_type] => utility [patent_app_number] => 11/488392 [patent_app_country] => US [patent_app_date] => 2006-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7327 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11488392 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/488392
Method and apparatus for integrating signal transition time modeling during routing Jul 17, 2006 Issued
Array ( [id] => 600491 [patent_doc_number] => 07437701 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-10-14 [patent_title] => 'Simulation of a programming language specification of a circuit design' [patent_app_type] => utility [patent_app_number] => 11/487898 [patent_app_country] => US [patent_app_date] => 2006-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5580 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/437/07437701.pdf [firstpage_image] =>[orig_patent_app_number] => 11487898 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/487898
Simulation of a programming language specification of a circuit design Jul 16, 2006 Issued
Array ( [id] => 355788 [patent_doc_number] => 07493585 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-02-17 [patent_title] => 'Methods of packing user logical RAM into dedicated RAM blocks and dual-use logic/RAM blocks' [patent_app_type] => utility [patent_app_number] => 11/486564 [patent_app_country] => US [patent_app_date] => 2006-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5458 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/493/07493585.pdf [firstpage_image] =>[orig_patent_app_number] => 11486564 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/486564
Methods of packing user logical RAM into dedicated RAM blocks and dual-use logic/RAM blocks Jul 12, 2006 Issued
Array ( [id] => 163564 [patent_doc_number] => 07676772 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-03-09 [patent_title] => 'Layout description having enhanced fill annotation' [patent_app_type] => utility [patent_app_number] => 11/486936 [patent_app_country] => US [patent_app_date] => 2006-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3058 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/676/07676772.pdf [firstpage_image] =>[orig_patent_app_number] => 11486936 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/486936
Layout description having enhanced fill annotation Jul 12, 2006 Issued
Array ( [id] => 290508 [patent_doc_number] => 07549134 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-06-16 [patent_title] => 'Method and system for performing crosstalk analysis' [patent_app_type] => utility [patent_app_number] => 11/479279 [patent_app_country] => US [patent_app_date] => 2006-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 3340 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/549/07549134.pdf [firstpage_image] =>[orig_patent_app_number] => 11479279 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/479279
Method and system for performing crosstalk analysis Jun 29, 2006 Issued
Array ( [id] => 5200877 [patent_doc_number] => 20070300195 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-27 [patent_title] => 'METHOD AND COMPUTER PROGRAM PRODUCT FOR INTERLAYER CONNECTION OF ARBITRARILY COMPLEX SHAPES UNDER ASYMMETRIC VIA ENCLOSURE RULES' [patent_app_type] => utility [patent_app_number] => 11/426223 [patent_app_country] => US [patent_app_date] => 2006-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5686 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0300/20070300195.pdf [firstpage_image] =>[orig_patent_app_number] => 11426223 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/426223
Method and computer program product for interlayer connection of arbitrarily complex shapes under asymmetric via enclosure rules Jun 22, 2006 Issued
Array ( [id] => 605178 [patent_doc_number] => 07434184 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-10-07 [patent_title] => 'Method for detecting flaws in a functional verification plan' [patent_app_type] => utility [patent_app_number] => 11/450701 [patent_app_country] => US [patent_app_date] => 2006-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 10449 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/434/07434184.pdf [firstpage_image] =>[orig_patent_app_number] => 11450701 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/450701
Method for detecting flaws in a functional verification plan Jun 8, 2006 Issued
Array ( [id] => 333376 [patent_doc_number] => 07512914 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-03-31 [patent_title] => 'Method of improving electronic component testability rate' [patent_app_type] => utility [patent_app_number] => 11/420727 [patent_app_country] => US [patent_app_date] => 2006-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1165 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/512/07512914.pdf [firstpage_image] =>[orig_patent_app_number] => 11420727 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/420727
Method of improving electronic component testability rate May 25, 2006 Issued
Array ( [id] => 846330 [patent_doc_number] => 07389479 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-06-17 [patent_title] => 'Formally proving the functional equivalence of pipelined designs containing memories' [patent_app_type] => utility [patent_app_number] => 11/436007 [patent_app_country] => US [patent_app_date] => 2006-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 6849 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/389/07389479.pdf [firstpage_image] =>[orig_patent_app_number] => 11436007 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/436007
Formally proving the functional equivalence of pipelined designs containing memories May 16, 2006 Issued
Array ( [id] => 598837 [patent_doc_number] => 07451417 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-11-11 [patent_title] => 'Timing annotation accuracy through the use of static timing analysis tools' [patent_app_type] => utility [patent_app_number] => 11/433127 [patent_app_country] => US [patent_app_date] => 2006-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5253 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/451/07451417.pdf [firstpage_image] =>[orig_patent_app_number] => 11433127 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/433127
Timing annotation accuracy through the use of static timing analysis tools May 11, 2006 Issued
Array ( [id] => 5706763 [patent_doc_number] => 20060195811 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-31 [patent_title] => 'SYSTEM AND METHOD FOR REDUCING DESIGN CYCLE TIME FOR DESIGNING INPUT/OUTPUT CELLS' [patent_app_type] => utility [patent_app_number] => 11/381042 [patent_app_country] => US [patent_app_date] => 2006-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3295 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0195/20060195811.pdf [firstpage_image] =>[orig_patent_app_number] => 11381042 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/381042
System and method for reducing design cycle time for designing input/output cells Apr 30, 2006 Issued
Array ( [id] => 5734772 [patent_doc_number] => 20060259889 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-16 [patent_title] => 'Method and apparatus for extending processing time in one pipeline stage' [patent_app_type] => utility [patent_app_number] => 11/414652 [patent_app_country] => US [patent_app_date] => 2006-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 57 [patent_figures_cnt] => 57 [patent_no_of_words] => 37529 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0259/20060259889.pdf [firstpage_image] =>[orig_patent_app_number] => 11414652 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/414652
Method and apparatus for extending processing time in one pipeline stage Apr 26, 2006 Issued
Array ( [id] => 5627178 [patent_doc_number] => 20060265683 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-23 [patent_title] => 'Circuit layout device, circuit layout method, and program for execution thereof' [patent_app_type] => utility [patent_app_number] => 11/411947 [patent_app_country] => US [patent_app_date] => 2006-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2457 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0265/20060265683.pdf [firstpage_image] =>[orig_patent_app_number] => 11411947 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/411947
Circuit layout device, circuit layout method, and program for execution thereof Apr 26, 2006 Issued
Array ( [id] => 5617348 [patent_doc_number] => 20060186880 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-24 [patent_title] => 'Automated drawing tool and method for drawing a sensor layout' [patent_app_type] => utility [patent_app_number] => 11/408290 [patent_app_country] => US [patent_app_date] => 2006-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 37 [patent_no_of_words] => 16452 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0186/20060186880.pdf [firstpage_image] =>[orig_patent_app_number] => 11408290 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/408290
Automated drawing tool and method for drawing a sensor layout Apr 19, 2006 Abandoned
Array ( [id] => 5832125 [patent_doc_number] => 20060243955 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-02 [patent_title] => 'Semiconductor integrated circuit device' [patent_app_type] => utility [patent_app_number] => 11/406987 [patent_app_country] => US [patent_app_date] => 2006-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3033 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0243/20060243955.pdf [firstpage_image] =>[orig_patent_app_number] => 11406987 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/406987
Semiconductor integrated circuit device Apr 18, 2006 Issued
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