
Brandon Bowers
Examiner (ID: 15542, Phone: (571)272-1888 , Office: P/2851 )
| Most Active Art Unit | 2851 |
| Art Unit(s) | 2825, 2851 |
| Total Applications | 903 |
| Issued Applications | 756 |
| Pending Applications | 52 |
| Abandoned Applications | 108 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4447711
[patent_doc_number] => 07930667
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-04-19
[patent_title] => 'System and method of automated wire and via layout optimization description'
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[pdf_file] => patents/07/930/07930667.pdf
[firstpage_image] =>[orig_patent_app_number] => 11465473
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/465473 | System and method of automated wire and via layout optimization description | Aug 17, 2006 | Issued |
Array
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[patent_doc_number] => 20080046848
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-02-21
[patent_title] => 'METHOD AND COMPUTER PROGRAM FOR STATIC TIMING ANALYSIS WITH DELAY DE-RATING AND CLOCK CONSERVATISM REDUCTION'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/465662 | Method and computer program for static timing analysis with delay de-rating and clock conservatism reduction | Aug 17, 2006 | Issued |
Array
(
[id] => 4659485
[patent_doc_number] => 20080028347
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[patent_issue_date] => 2008-01-31
[patent_title] => 'Transformation of IC designs for formal verification'
[patent_app_type] => utility
[patent_app_number] => 11/495136
[patent_app_country] => US
[patent_app_date] => 2006-07-28
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/495136 | Transformation of IC designs for formal verification | Jul 27, 2006 | Issued |
Array
(
[id] => 5206715
[patent_doc_number] => 20070028197
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[patent_kind] => A1
[patent_issue_date] => 2007-02-01
[patent_title] => 'METHOD AND APPARATUS FOR AUTO-GENERATION OF SHIFT REGISTER FILE FOR HIGH-LEVEL SYNTHESIS COMPILER'
[patent_app_type] => utility
[patent_app_number] => 11/460396
[patent_app_country] => US
[patent_app_date] => 2006-07-27
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/460396 | METHOD AND APPARATUS FOR AUTO-GENERATION OF SHIFT REGISTER FILE FOR HIGH-LEVEL SYNTHESIS COMPILER | Jul 26, 2006 | Abandoned |
Array
(
[id] => 5161763
[patent_doc_number] => 20070174807
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[patent_issue_date] => 2007-07-26
[patent_title] => 'Semiconductor device manufacturing method, library used for the same, recording medium, and semiconductor device manufacturing system'
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Array
(
[id] => 10873388
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[patent_issue_date] => 2014-11-25
[patent_title] => 'Method and apparatus for integrating signal transition time modeling during routing'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/488392 | Method and apparatus for integrating signal transition time modeling during routing | Jul 17, 2006 | Issued |
Array
(
[id] => 600491
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[patent_title] => 'Simulation of a programming language specification of a circuit design'
[patent_app_type] => utility
[patent_app_number] => 11/487898
[patent_app_country] => US
[patent_app_date] => 2006-07-17
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/487898 | Simulation of a programming language specification of a circuit design | Jul 16, 2006 | Issued |
Array
(
[id] => 355788
[patent_doc_number] => 07493585
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2009-02-17
[patent_title] => 'Methods of packing user logical RAM into dedicated RAM blocks and dual-use logic/RAM blocks'
[patent_app_type] => utility
[patent_app_number] => 11/486564
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/486564 | Methods of packing user logical RAM into dedicated RAM blocks and dual-use logic/RAM blocks | Jul 12, 2006 | Issued |
Array
(
[id] => 163564
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[patent_issue_date] => 2010-03-09
[patent_title] => 'Layout description having enhanced fill annotation'
[patent_app_type] => utility
[patent_app_number] => 11/486936
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/486936 | Layout description having enhanced fill annotation | Jul 12, 2006 | Issued |
Array
(
[id] => 290508
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[patent_issue_date] => 2009-06-16
[patent_title] => 'Method and system for performing crosstalk analysis'
[patent_app_type] => utility
[patent_app_number] => 11/479279
[patent_app_country] => US
[patent_app_date] => 2006-06-30
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/479279 | Method and system for performing crosstalk analysis | Jun 29, 2006 | Issued |
Array
(
[id] => 5200877
[patent_doc_number] => 20070300195
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[patent_title] => 'METHOD AND COMPUTER PROGRAM PRODUCT FOR INTERLAYER CONNECTION OF ARBITRARILY COMPLEX SHAPES UNDER ASYMMETRIC VIA ENCLOSURE RULES'
[patent_app_type] => utility
[patent_app_number] => 11/426223
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/426223 | Method and computer program product for interlayer connection of arbitrarily complex shapes under asymmetric via enclosure rules | Jun 22, 2006 | Issued |
Array
(
[id] => 605178
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[patent_title] => 'Method for detecting flaws in a functional verification plan'
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Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/420727 | Method of improving electronic component testability rate | May 25, 2006 | Issued |
Array
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Array
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Array
(
[id] => 5706763
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Array
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Array
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Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/406987 | Semiconductor integrated circuit device | Apr 18, 2006 | Issued |