Brandon Bowers

Array ( [id] => 5249048 [patent_doc_number] => 20070245282 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-18 [patent_title] => 'Systems, Methods, and Media for Using Relative Positioning in Structures with Dynamic Ranges' [patent_app_type] => utility [patent_app_number] => 11/279237 [patent_app_country] => US [patent_app_date] => 2006-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7212 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0245/20070245282.pdf [firstpage_image] =>[orig_patent_app_number] => 11279237 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 597245 [patent_doc_number] => 07454734 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-11-18 [patent_title] => 'Method of designing layout of semiconductor integrated circuit and apparatus for doing the same' [patent_app_type] => utility [patent_app_number] => 11/376178 [patent_app_country] => US [patent_app_date] => 2006-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 13881 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/454/07454734.pdf [firstpage_image] =>[orig_patent_app_number] => 11376178 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8472872 [patent_doc_number] => 08302065 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-30 [patent_title] => 'Device and method for testing a device' [patent_app_type] => utility [patent_app_number] => 12/281927 [patent_app_country] => US [patent_app_date] => 2006-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4215 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12281927 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 599512 [patent_doc_number] => 07444602 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-10-28 [patent_title] => 'Method of generating ASIC design database' [patent_app_type] => utility [patent_app_number] => 11/352288 [patent_app_country] => US [patent_app_date] => 2006-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 1934 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 274 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/444/07444602.pdf [firstpage_image] =>[orig_patent_app_number] => 11352288 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 347183 [patent_doc_number] => 07500213 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-03-03 [patent_title] => 'Array-based architecture for molecular electronics' [patent_app_type] => utility [patent_app_number] => 11/344884 [patent_app_country] => US [patent_app_date] => 2006-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 6187 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/500/07500213.pdf [firstpage_image] =>[orig_patent_app_number] => 11344884 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 261953 [patent_doc_number] => 07574687 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-08-11 [patent_title] => 'Method and system to optimize timing margin in a system in package module' [patent_app_type] => utility [patent_app_number] => 11/325027 [patent_app_country] => US [patent_app_date] => 2006-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3403 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/574/07574687.pdf [firstpage_image] =>[orig_patent_app_number] => 11325027 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5777949 [patent_doc_number] => 20060106589 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-18 [patent_title] => 'Integrated circuit design using charge pump modeling' [patent_app_type] => utility [patent_app_number] => 11/300034 [patent_app_country] => US [patent_app_date] => 2005-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4134 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0106/20060106589.pdf [firstpage_image] =>[orig_patent_app_number] => 11300034 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5615348 [patent_doc_number] => 20060117277 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-01 [patent_title] => 'Circuit design support methods and systems' [patent_app_type] => utility [patent_app_number] => 11/288307 [patent_app_country] => US [patent_app_date] => 2005-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4761 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0117/20060117277.pdf [firstpage_image] =>[orig_patent_app_number] => 11288307 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5190700 [patent_doc_number] => 20070169009 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-19 [patent_title] => 'Method and system for outputting a sequence of commands and data described by a flowchart' [patent_app_type] => utility [patent_app_number] => 11/260517 [patent_app_country] => US [patent_app_date] => 2005-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4580 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0169/20070169009.pdf [firstpage_image] =>[orig_patent_app_number] => 11260517 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 107093 [patent_doc_number] => 07730437 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-06-01 [patent_title] => 'Method of full semiconductor chip timing closure' [patent_app_type] => utility [patent_app_number] => 11/256807 [patent_app_country] => US [patent_app_date] => 2005-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3748 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/730/07730437.pdf [firstpage_image] =>[orig_patent_app_number] => 11256807 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 600480 [patent_doc_number] => 07437690 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-10-14 [patent_title] => 'Method for predicate-based compositional minimization in a verification environment' [patent_app_type] => utility [patent_app_number] => 11/249937 [patent_app_country] => US [patent_app_date] => 2005-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 7684 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/437/07437690.pdf [firstpage_image] =>[orig_patent_app_number] => 11249937 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 836491 [patent_doc_number] => 07398487 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-07-08 [patent_title] => 'Programmable logic device-structured application specific integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/205528 [patent_app_country] => US [patent_app_date] => 2005-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3534 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/398/07398487.pdf [firstpage_image] =>[orig_patent_app_number] => 11205528 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 836517 [patent_doc_number] => 07398504 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-07-08 [patent_title] => 'Program, method and apparatus for analyzing transmission signals' [patent_app_type] => utility [patent_app_number] => 11/203118 [patent_app_country] => US [patent_app_date] => 2005-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 51 [patent_no_of_words] => 7186 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/398/07398504.pdf [firstpage_image] =>[orig_patent_app_number] => 11203118 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 87963 [patent_doc_number] => 07743358 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-22 [patent_title] => 'Apparatus and method for segmenting edges for optical proximity correction' [patent_app_type] => utility [patent_app_number] => 11/203498 [patent_app_country] => US [patent_app_date] => 2005-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 7570 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/743/07743358.pdf [firstpage_image] =>[orig_patent_app_number] => 11203498 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 368916 [patent_doc_number] => 07480891 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-01-20 [patent_title] => 'Method and apparatus of model-based photomask synthesis' [patent_app_type] => utility [patent_app_number] => 11/203505 [patent_app_country] => US [patent_app_date] => 2005-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 17 [patent_no_of_words] => 9456 [patent_no_of_claims] => 55 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/480/07480891.pdf [firstpage_image] =>[orig_patent_app_number] => 11203505 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 891063 [patent_doc_number] => 07353485 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-04-01 [patent_title] => 'Method of flexible clock placement for integrated circuit designs using integer linear programming' [patent_app_type] => utility [patent_app_number] => 11/200627 [patent_app_country] => US [patent_app_date] => 2005-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 4680 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/353/07353485.pdf [firstpage_image] =>[orig_patent_app_number] => 11200627 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 276140 [patent_doc_number] => 07562315 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-07-14 [patent_title] => 'Edge recognition based high voltage pseudo layer verification methodology for mix signal design layout' [patent_app_type] => utility [patent_app_number] => 11/199337 [patent_app_country] => US [patent_app_date] => 2005-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3597 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/562/07562315.pdf [firstpage_image] =>[orig_patent_app_number] => 11199337 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5881055 [patent_doc_number] => 20060030138 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-09 [patent_title] => 'Layout method for semiconductor integrated circuit device' [patent_app_type] => utility [patent_app_number] => 11/197307 [patent_app_country] => US [patent_app_date] => 2005-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3304 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0030/20060030138.pdf [firstpage_image] =>[orig_patent_app_number] => 11197307 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5150539 [patent_doc_number] => 20070050599 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-01 [patent_title] => 'Determining the placement of semiconductor components on an integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/189227 [patent_app_country] => US [patent_app_date] => 2005-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4771 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0050/20070050599.pdf [firstpage_image] =>[orig_patent_app_number] => 11189227 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5830798 [patent_doc_number] => 20060064678 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-23 [patent_title] => 'Debugger of an electric circuit manufactured based on a program in harware description language' [patent_app_type] => utility [patent_app_number] => 11/187627 [patent_app_country] => US [patent_app_date] => 2005-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4368 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0064/20060064678.pdf [firstpage_image] =>[orig_patent_app_number] => 11187627 [rel_patent_id] =>[rel_patent_doc_number] =>)