Search

Brandon Bowers

Examiner (ID: 10602, Phone: (571)272-1888 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2825, 2851
Total Applications
889
Issued Applications
747
Pending Applications
56
Abandoned Applications
107

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18695224 [patent_doc_number] => 20230325645 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-12 [patent_title] => ARTIFICIAL NEURAL NETWORK COMPRISING A THREE-DIMENSIONAL INTEGRATED CIRCUIT [patent_app_type] => utility [patent_app_number] => 17/848371 [patent_app_country] => US [patent_app_date] => 2022-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17501 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -45 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17848371 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/848371
ARTIFICIAL NEURAL NETWORK COMPRISING A THREE-DIMENSIONAL INTEGRATED CIRCUIT Jun 22, 2022 Pending
Array ( [id] => 19942519 [patent_doc_number] => 12314651 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2025-05-27 [patent_title] => Zigzag detection and handling for integrated circuit design [patent_app_type] => utility [patent_app_number] => 17/831328 [patent_app_country] => US [patent_app_date] => 2022-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 980 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17831328 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/831328
Zigzag detection and handling for integrated circuit design Jun 1, 2022 Issued
Array ( [id] => 17839249 [patent_doc_number] => 20220276554 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-01 [patent_title] => Enforcing mask synthesis consistency across random areas of integrated circuit chips [patent_app_type] => utility [patent_app_number] => 17/749952 [patent_app_country] => US [patent_app_date] => 2022-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12035 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17749952 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/749952
Enforcing mask synthesis consistency across random areas of integrated circuit chips May 19, 2022 Issued
Array ( [id] => 18061767 [patent_doc_number] => 20220392854 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-08 [patent_title] => INTEGRATED CIRCUIT WITH INTENTIONAL RADIATION INTOLERANCE [patent_app_type] => utility [patent_app_number] => 17/742925 [patent_app_country] => US [patent_app_date] => 2022-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9965 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17742925 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/742925
INTEGRATED CIRCUIT WITH INTENTIONAL RADIATION INTOLERANCE May 11, 2022 Abandoned
Array ( [id] => 18773115 [patent_doc_number] => 20230367944 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-16 [patent_title] => CIRCUITRY ARRANGEMENT IN A FLOORPLAN OF A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/740705 [patent_app_country] => US [patent_app_date] => 2022-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11756 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17740705 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/740705
CIRCUITRY ARRANGEMENT IN A FLOORPLAN OF A MEMORY DEVICE May 9, 2022 Pending
Array ( [id] => 17794492 [patent_doc_number] => 20220253584 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-11 [patent_title] => OVER-THE-AIR HARDWARE UPDATE [patent_app_type] => utility [patent_app_number] => 17/660605 [patent_app_country] => US [patent_app_date] => 2022-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7902 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17660605 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/660605
Over-the-air hardware update Apr 24, 2022 Issued
Array ( [id] => 18668815 [patent_doc_number] => 11775719 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-10-03 [patent_title] => Cell instance charge model for delay calculation [patent_app_type] => utility [patent_app_number] => 17/713004 [patent_app_country] => US [patent_app_date] => 2022-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8279 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17713004 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/713004
Cell instance charge model for delay calculation Apr 3, 2022 Issued
Array ( [id] => 18281308 [patent_doc_number] => 20230096780 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-30 [patent_title] => DETECTING CIRCUIT AND A DETECTING SYSTEM OF A BACK-UP ENERGY-STORING SYSTEM AND RELATED DETECTING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/704386 [patent_app_country] => US [patent_app_date] => 2022-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4185 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 326 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17704386 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/704386
DETECTING CIRCUIT AND A DETECTING SYSTEM OF A BACK-UP ENERGY-STORING SYSTEM AND RELATED DETECTING METHOD THEREOF Mar 24, 2022 Abandoned
Array ( [id] => 19857326 [patent_doc_number] => 12260164 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-25 [patent_title] => Method for designing pattern layout including oblique edges and method for manufacturing semiconductor device using the same [patent_app_type] => utility [patent_app_number] => 17/703338 [patent_app_country] => US [patent_app_date] => 2022-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 20 [patent_no_of_words] => 8579 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17703338 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/703338
Method for designing pattern layout including oblique edges and method for manufacturing semiconductor device using the same Mar 23, 2022 Issued
Array ( [id] => 17896260 [patent_doc_number] => 20220305922 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-29 [patent_title] => SYSTEM AND METHOD FOR BATTERY MODULE REPLACEMENT [patent_app_type] => utility [patent_app_number] => 17/702024 [patent_app_country] => US [patent_app_date] => 2022-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5920 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17702024 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/702024
SYSTEM AND METHOD FOR BATTERY MODULE REPLACEMENT Mar 22, 2022 Pending
Array ( [id] => 17896269 [patent_doc_number] => 20220305931 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-29 [patent_title] => CHARGING FACILITY AND METHOD OF CONTROLLING CHARGING FACILITY [patent_app_type] => utility [patent_app_number] => 17/699182 [patent_app_country] => US [patent_app_date] => 2022-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4194 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17699182 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/699182
CHARGING FACILITY AND METHOD OF CONTROLLING CHARGING FACILITY Mar 20, 2022 Pending
Array ( [id] => 17896269 [patent_doc_number] => 20220305931 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-29 [patent_title] => CHARGING FACILITY AND METHOD OF CONTROLLING CHARGING FACILITY [patent_app_type] => utility [patent_app_number] => 17/699182 [patent_app_country] => US [patent_app_date] => 2022-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4194 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17699182 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/699182
CHARGING FACILITY AND METHOD OF CONTROLLING CHARGING FACILITY Mar 20, 2022 Pending
Array ( [id] => 20266140 [patent_doc_number] => 12437133 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-07 [patent_title] => Property-driven automatic generation of reduced component hardware [patent_app_type] => utility [patent_app_number] => 17/695387 [patent_app_country] => US [patent_app_date] => 2022-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 7723 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17695387 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/695387
Property-driven automatic generation of reduced component hardware Mar 14, 2022 Issued
Array ( [id] => 20266140 [patent_doc_number] => 12437133 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-07 [patent_title] => Property-driven automatic generation of reduced component hardware [patent_app_type] => utility [patent_app_number] => 17/695387 [patent_app_country] => US [patent_app_date] => 2022-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 7723 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17695387 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/695387
Property-driven automatic generation of reduced component hardware Mar 14, 2022 Issued
Array ( [id] => 17871513 [patent_doc_number] => 20220294250 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-15 [patent_title] => POWER SYSTEM, MONITORING DEVICE, INVERTER DEVICE AND PROGRAM [patent_app_type] => utility [patent_app_number] => 17/694374 [patent_app_country] => US [patent_app_date] => 2022-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19693 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 267 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17694374 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/694374
Power system, monitoring device, inverter device and program Mar 13, 2022 Issued
Array ( [id] => 18826853 [patent_doc_number] => 11842132 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-12-12 [patent_title] => Multi-cycle power analysis of integrated circuit designs [patent_app_type] => utility [patent_app_number] => 17/690992 [patent_app_country] => US [patent_app_date] => 2022-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 20823 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17690992 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/690992
Multi-cycle power analysis of integrated circuit designs Mar 8, 2022 Issued
Array ( [id] => 18614634 [patent_doc_number] => 20230281371 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-07 [patent_title] => METHOD OF WARPAGE-AWARE FLOORPLANNING FOR HETEROGENEOUS INTEGRATION STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/683826 [patent_app_country] => US [patent_app_date] => 2022-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6413 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17683826 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/683826
Method of warpage-aware floorplanning for heterogeneous integration structure Feb 28, 2022 Issued
Array ( [id] => 18614634 [patent_doc_number] => 20230281371 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-07 [patent_title] => METHOD OF WARPAGE-AWARE FLOORPLANNING FOR HETEROGENEOUS INTEGRATION STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/683826 [patent_app_country] => US [patent_app_date] => 2022-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6413 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17683826 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/683826
Method of warpage-aware floorplanning for heterogeneous integration structure Feb 28, 2022 Issued
Array ( [id] => 18599256 [patent_doc_number] => 20230274056 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-31 [patent_title] => Method for Parallelism-Aware Wavelength-Routed Optical Networks-on-Chip Design [patent_app_type] => utility [patent_app_number] => 17/682384 [patent_app_country] => US [patent_app_date] => 2022-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7769 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17682384 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/682384
Method for parallelism-aware wavelength-routed optical networks-on-chip design Feb 27, 2022 Issued
Array ( [id] => 18291561 [patent_doc_number] => 11620431 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-04 [patent_title] => System and method for performing depth-dependent oxidation modeling in a virtual fabrication environment [patent_app_type] => utility [patent_app_number] => 17/682364 [patent_app_country] => US [patent_app_date] => 2022-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 10949 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17682364 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/682364
System and method for performing depth-dependent oxidation modeling in a virtual fabrication environment Feb 27, 2022 Issued
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