Search

Brandon Bowers

Examiner (ID: 3343)

Most Active Art Unit
2851
Art Unit(s)
2825, 2851
Total Applications
898
Issued Applications
755
Pending Applications
50
Abandoned Applications
108

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17840793 [patent_doc_number] => 20220278099 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-01 [patent_title] => CIRCUITS DESIGNED AND MANUFACTURED WITH FIRST AND SECOND DESIGN RULES [patent_app_type] => utility [patent_app_number] => 17/542014 [patent_app_country] => US [patent_app_date] => 2021-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12352 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17542014 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/542014
Circuits designed and manufactured with first and second design rules Dec 2, 2021 Issued
Array ( [id] => 18591657 [patent_doc_number] => 11740550 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-29 [patent_title] => Method of performing optical proximity correction and method of manufacturing lithographic mask by using the same [patent_app_type] => utility [patent_app_number] => 17/534506 [patent_app_country] => US [patent_app_date] => 2021-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 7971 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17534506 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/534506
Method of performing optical proximity correction and method of manufacturing lithographic mask by using the same Nov 23, 2021 Issued
Array ( [id] => 17580271 [patent_doc_number] => 20220137126 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-05 [patent_title] => REFORMATTING SCAN PATTERNS IN PRESENCE OF HOLD TYPE PIPELINES [patent_app_type] => utility [patent_app_number] => 17/518024 [patent_app_country] => US [patent_app_date] => 2021-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5976 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17518024 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/518024
Reformatting scan patterns in presence of hold type pipelines Nov 2, 2021 Issued
Array ( [id] => 18839326 [patent_doc_number] => 11847400 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-19 [patent_title] => Methods and systems for generating shape data for electronic designs [patent_app_type] => utility [patent_app_number] => 17/453321 [patent_app_country] => US [patent_app_date] => 2021-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5072 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17453321 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/453321
Methods and systems for generating shape data for electronic designs Nov 1, 2021 Issued
Array ( [id] => 19951330 [patent_doc_number] => 12322701 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-03 [patent_title] => Different scaling ratio in FEOL / MOL/ BEOL [patent_app_type] => utility [patent_app_number] => 17/501371 [patent_app_country] => US [patent_app_date] => 2021-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17501371 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/501371
Different scaling ratio in FEOL / MOL/ BEOL Oct 13, 2021 Issued
Array ( [id] => 20441687 [patent_doc_number] => 12512529 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-30 [patent_title] => Air-cooled battery pack for electric vehicle [patent_app_type] => utility [patent_app_number] => 17/797319 [patent_app_country] => US [patent_app_date] => 2021-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 0 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17797319 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/797319
Air-cooled battery pack for electric vehicle Oct 12, 2021 Issued
Array ( [id] => 17369275 [patent_doc_number] => 20220024327 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-27 [patent_title] => AUTOMOBILE CHARGER [patent_app_type] => utility [patent_app_number] => 17/495196 [patent_app_country] => US [patent_app_date] => 2021-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2218 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17495196 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/495196
Automobile charger Oct 5, 2021 Issued
Array ( [id] => 18286033 [patent_doc_number] => 20230101505 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-30 [patent_title] => QUANTUM FIELD-PROGRAMMABLE ANALOG ARRAYS AND RELATED METHODS AND SYSTEMS [patent_app_type] => utility [patent_app_number] => 17/490641 [patent_app_country] => US [patent_app_date] => 2021-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5552 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17490641 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/490641
QUANTUM FIELD-PROGRAMMABLE ANALOG ARRAYS AND RELATED METHODS AND SYSTEMS Sep 29, 2021 Pending
Array ( [id] => 19626015 [patent_doc_number] => 12164848 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-10 [patent_title] => Technologies for circuit design [patent_app_type] => utility [patent_app_number] => 17/485296 [patent_app_country] => US [patent_app_date] => 2021-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 31 [patent_no_of_words] => 25479 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17485296 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/485296
Technologies for circuit design Sep 23, 2021 Issued
Array ( [id] => 19740141 [patent_doc_number] => 12216976 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-04 [patent_title] => Efficient integrated circuit simulation and testing [patent_app_type] => utility [patent_app_number] => 17/485168 [patent_app_country] => US [patent_app_date] => 2021-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 6434 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17485168 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/485168
Efficient integrated circuit simulation and testing Sep 23, 2021 Issued
Array ( [id] => 18207454 [patent_doc_number] => 20230053711 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-23 [patent_title] => INTEGRATED CIRCUIT DEVICE DESIGN METHOD AND SYSTEM [patent_app_type] => utility [patent_app_number] => 17/480358 [patent_app_country] => US [patent_app_date] => 2021-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9920 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17480358 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/480358
Integrated circuit device design method and system Sep 20, 2021 Issued
Array ( [id] => 18826859 [patent_doc_number] => 11842138 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-12 [patent_title] => Integrated routing assembly and system using same [patent_app_type] => utility [patent_app_number] => 17/477542 [patent_app_country] => US [patent_app_date] => 2021-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 36 [patent_no_of_words] => 6568 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17477542 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/477542
Integrated routing assembly and system using same Sep 16, 2021 Issued
Array ( [id] => 18079845 [patent_doc_number] => 20220405457 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-22 [patent_title] => Standard Cell Design [patent_app_type] => utility [patent_app_number] => 17/476615 [patent_app_country] => US [patent_app_date] => 2021-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8196 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17476615 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/476615
Standard cell design Sep 15, 2021 Issued
Array ( [id] => 17932144 [patent_doc_number] => 20220327269 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-13 [patent_title] => COMPUTING DEVICE AND METHOD FOR DETECTING CLOCK DOMAIN CROSSING VIOLATION IN DESIGN OF MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/475107 [patent_app_country] => US [patent_app_date] => 2021-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4866 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17475107 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/475107
Computing device and method for detecting clock domain crossing violation in design of memory device Sep 13, 2021 Issued
Array ( [id] => 17484746 [patent_doc_number] => 20220092250 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-24 [patent_title] => CHIP, LAYOUT DESIGN SYSTEM, AND LAYOUT DESIGN METHOD [patent_app_type] => utility [patent_app_number] => 17/474085 [patent_app_country] => US [patent_app_date] => 2021-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4971 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17474085 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/474085
Chip, layout design system, and layout design method Sep 13, 2021 Issued
Array ( [id] => 18253424 [patent_doc_number] => 20230080463 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-16 [patent_title] => METHODS AND SYSTEMS FOR IDENTIFYING FLAWS AND BUGS IN INTEGRATED CIRCUITS, FOR EXAMPLE, MICROPROCESSORS [patent_app_type] => utility [patent_app_number] => 17/473393 [patent_app_country] => US [patent_app_date] => 2021-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8922 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17473393 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/473393
Methods and systems for identifying flaws and bugs in integrated circuits, for example, microprocessors Sep 12, 2021 Issued
Array ( [id] => 18243459 [patent_doc_number] => 20230075770 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-09 [patent_title] => CLOCK MAPPING IN AN INTEGRATED CIRCUIT DESIGN [patent_app_type] => utility [patent_app_number] => 17/468304 [patent_app_country] => US [patent_app_date] => 2021-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 26871 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17468304 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/468304
Clock mapping in an integrated circuit design Sep 6, 2021 Issued
Array ( [id] => 18229286 [patent_doc_number] => 20230068280 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => INTEGRATED CIRCUIT DEVICE AND METHOD [patent_app_type] => utility [patent_app_number] => 17/463203 [patent_app_country] => US [patent_app_date] => 2021-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 23288 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17463203 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/463203
Integrated circuit device and method Aug 30, 2021 Issued
Array ( [id] => 18230594 [patent_doc_number] => 20230069588 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => VARIANT MODEL-BASED COMPILATION FOR ANALOG SIMULATION [patent_app_type] => utility [patent_app_number] => 17/412404 [patent_app_country] => US [patent_app_date] => 2021-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4229 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17412404 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/412404
Variant model-based compilation for analog simulation Aug 25, 2021 Issued
Array ( [id] => 18966264 [patent_doc_number] => 11900034 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-13 [patent_title] => Method of modeling a component fault tree for an electric circuit [patent_app_type] => utility [patent_app_number] => 17/408653 [patent_app_country] => US [patent_app_date] => 2021-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 5506 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 360 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17408653 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/408653
Method of modeling a component fault tree for an electric circuit Aug 22, 2021 Issued
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