
Brandon Bowers
Examiner (ID: 10602, Phone: (571)272-1888 , Office: P/2851 )
| Most Active Art Unit | 2851 |
| Art Unit(s) | 2825, 2851 |
| Total Applications | 889 |
| Issued Applications | 747 |
| Pending Applications | 56 |
| Abandoned Applications | 107 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 17932144
[patent_doc_number] => 20220327269
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-10-13
[patent_title] => COMPUTING DEVICE AND METHOD FOR DETECTING CLOCK DOMAIN CROSSING VIOLATION IN DESIGN OF MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/475107
[patent_app_country] => US
[patent_app_date] => 2021-09-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4866
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17475107
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/475107 | Computing device and method for detecting clock domain crossing violation in design of memory device | Sep 13, 2021 | Issued |
Array
(
[id] => 17484746
[patent_doc_number] => 20220092250
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-03-24
[patent_title] => CHIP, LAYOUT DESIGN SYSTEM, AND LAYOUT DESIGN METHOD
[patent_app_type] => utility
[patent_app_number] => 17/474085
[patent_app_country] => US
[patent_app_date] => 2021-09-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4971
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17474085
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/474085 | Chip, layout design system, and layout design method | Sep 13, 2021 | Issued |
Array
(
[id] => 18253424
[patent_doc_number] => 20230080463
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-03-16
[patent_title] => METHODS AND SYSTEMS FOR IDENTIFYING FLAWS AND BUGS IN INTEGRATED CIRCUITS, FOR EXAMPLE, MICROPROCESSORS
[patent_app_type] => utility
[patent_app_number] => 17/473393
[patent_app_country] => US
[patent_app_date] => 2021-09-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8922
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17473393
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/473393 | Methods and systems for identifying flaws and bugs in integrated circuits, for example, microprocessors | Sep 12, 2021 | Issued |
Array
(
[id] => 18243459
[patent_doc_number] => 20230075770
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-03-09
[patent_title] => CLOCK MAPPING IN AN INTEGRATED CIRCUIT DESIGN
[patent_app_type] => utility
[patent_app_number] => 17/468304
[patent_app_country] => US
[patent_app_date] => 2021-09-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 26871
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -21
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17468304
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/468304 | Clock mapping in an integrated circuit design | Sep 6, 2021 | Issued |
Array
(
[id] => 18229286
[patent_doc_number] => 20230068280
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-03-02
[patent_title] => INTEGRATED CIRCUIT DEVICE AND METHOD
[patent_app_type] => utility
[patent_app_number] => 17/463203
[patent_app_country] => US
[patent_app_date] => 2021-08-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 23288
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 150
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17463203
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/463203 | Integrated circuit device and method | Aug 30, 2021 | Issued |
Array
(
[id] => 18230594
[patent_doc_number] => 20230069588
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-03-02
[patent_title] => VARIANT MODEL-BASED COMPILATION FOR ANALOG SIMULATION
[patent_app_type] => utility
[patent_app_number] => 17/412404
[patent_app_country] => US
[patent_app_date] => 2021-08-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4229
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 103
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17412404
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/412404 | Variant model-based compilation for analog simulation | Aug 25, 2021 | Issued |
Array
(
[id] => 18966264
[patent_doc_number] => 11900034
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-02-13
[patent_title] => Method of modeling a component fault tree for an electric circuit
[patent_app_type] => utility
[patent_app_number] => 17/408653
[patent_app_country] => US
[patent_app_date] => 2021-08-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 9
[patent_no_of_words] => 5506
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 360
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17408653
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/408653 | Method of modeling a component fault tree for an electric circuit | Aug 22, 2021 | Issued |
Array
(
[id] => 17478116
[patent_doc_number] => 20220085620
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-03-17
[patent_title] => METHODS AND APARATUSES FOR CHARGING HYBRID BATTERY PACK
[patent_app_type] => utility
[patent_app_number] => 17/402875
[patent_app_country] => US
[patent_app_date] => 2021-08-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11821
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 117
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17402875
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/402875 | Methods and aparatuses for charging hybrid battery pack | Aug 15, 2021 | Issued |
Array
(
[id] => 18197918
[patent_doc_number] => 20230051437
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-02-16
[patent_title] => ENHANCED QUANTUM CIRCUIT OPERATION VIA A UNIVERSALLY IMPLEMENTABLE 4X4 UNITARY MATRIX DECOMPOSITION
[patent_app_type] => utility
[patent_app_number] => 17/400677
[patent_app_country] => US
[patent_app_date] => 2021-08-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 19194
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 59
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17400677
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/400677 | Enhanced quantum circuit operation via a universally implementable 4X4 unitary matrix decomposition | Aug 11, 2021 | Issued |
Array
(
[id] => 19493398
[patent_doc_number] => 12112114
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-10-08
[patent_title] => Hierarchical color decomposition of library cells with boundary-aware color selection
[patent_app_type] => utility
[patent_app_number] => 17/399397
[patent_app_country] => US
[patent_app_date] => 2021-08-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 10
[patent_no_of_words] => 8829
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 174
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17399397
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/399397 | Hierarchical color decomposition of library cells with boundary-aware color selection | Aug 10, 2021 | Issued |
Array
(
[id] => 18154151
[patent_doc_number] => 11567126
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-01-31
[patent_title] => Methods and systems for fault injection testing of an integrated circuit hardware design
[patent_app_type] => utility
[patent_app_number] => 17/444095
[patent_app_country] => US
[patent_app_date] => 2021-07-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 16056
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 272
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17444095
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/444095 | Methods and systems for fault injection testing of an integrated circuit hardware design | Jul 29, 2021 | Issued |
Array
(
[id] => 19122691
[patent_doc_number] => 11966680
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-04-23
[patent_title] => Noise simulation system
[patent_app_type] => utility
[patent_app_number] => 17/378799
[patent_app_country] => US
[patent_app_date] => 2021-07-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3660
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17378799
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/378799 | Noise simulation system | Jul 18, 2021 | Issued |
Array
(
[id] => 18144915
[patent_doc_number] => 20230018768
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-01-19
[patent_title] => METHODS AND SYSTEMS FOR PRINTED CIRCUIT BOARD PHYSICAL OUTLINE ESTIMATION AND APPROVAL
[patent_app_type] => utility
[patent_app_number] => 17/376204
[patent_app_country] => US
[patent_app_date] => 2021-07-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 20467
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -30
[patent_words_short_claim] => 80
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17376204
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/376204 | Methods and systems for printed circuit board physical outline estimation and approval | Jul 14, 2021 | Issued |
Array
(
[id] => 19508242
[patent_doc_number] => 12119674
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-10-15
[patent_title] => Display device and electronic device including the same
[patent_app_type] => utility
[patent_app_number] => 17/363902
[patent_app_country] => US
[patent_app_date] => 2021-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 19
[patent_no_of_words] => 13119
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 204
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17363902
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/363902 | Display device and electronic device including the same | Jun 29, 2021 | Issued |
Array
(
[id] => 18108935
[patent_doc_number] => 20230001815
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-01-05
[patent_title] => DRAIN-ASSISTED SUPPLY GENERATION CIRCUITS
[patent_app_type] => utility
[patent_app_number] => 17/364652
[patent_app_country] => US
[patent_app_date] => 2021-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12543
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -21
[patent_words_short_claim] => 46
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17364652
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/364652 | DRAIN-ASSISTED SUPPLY GENERATION CIRCUITS | Jun 29, 2021 | Pending |
Array
(
[id] => 19829055
[patent_doc_number] => 12249852
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-03-11
[patent_title] => Cart gate
[patent_app_type] => utility
[patent_app_number] => 17/363709
[patent_app_country] => US
[patent_app_date] => 2021-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 7513
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 282
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17363709
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/363709 | Cart gate | Jun 29, 2021 | Issued |
Array
(
[id] => 19703965
[patent_doc_number] => 12198002
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-01-14
[patent_title] => System and method for optimizing quantum circuit synthesis
[patent_app_type] => utility
[patent_app_number] => 17/304421
[patent_app_country] => US
[patent_app_date] => 2021-06-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 14
[patent_no_of_words] => 16883
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17304421
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/304421 | System and method for optimizing quantum circuit synthesis | Jun 20, 2021 | Issued |
Array
(
[id] => 18918363
[patent_doc_number] => 11880643
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-01-23
[patent_title] => Device and method for integrated circuit assistance design, and method for constructing electrical performance gradient model
[patent_app_type] => utility
[patent_app_number] => 17/349877
[patent_app_country] => US
[patent_app_date] => 2021-06-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 3185
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 113
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17349877
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/349877 | Device and method for integrated circuit assistance design, and method for constructing electrical performance gradient model | Jun 15, 2021 | Issued |
Array
(
[id] => 19293540
[patent_doc_number] => 12032894
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-07-09
[patent_title] => System and method for synchronizing net text across hierarchical levels
[patent_app_type] => utility
[patent_app_number] => 17/349250
[patent_app_country] => US
[patent_app_date] => 2021-06-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 6297
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 127
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17349250
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/349250 | System and method for synchronizing net text across hierarchical levels | Jun 15, 2021 | Issued |
Array
(
[id] => 18856087
[patent_doc_number] => 11853671
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2023-12-26
[patent_title] => Filling vacant areas of an integrated circuit design
[patent_app_type] => utility
[patent_app_number] => 17/342251
[patent_app_country] => US
[patent_app_date] => 2021-06-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 16
[patent_no_of_words] => 9237
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 139
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17342251
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/342251 | Filling vacant areas of an integrated circuit design | Jun 7, 2021 | Issued |