
Brandon Bowers
Examiner (ID: 3343)
| Most Active Art Unit | 2851 |
| Art Unit(s) | 2825, 2851 |
| Total Applications | 898 |
| Issued Applications | 755 |
| Pending Applications | 50 |
| Abandoned Applications | 108 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 18430722
[patent_doc_number] => 11675944
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-06-13
[patent_title] => Power reduction in very large-scale integration (VLSI) systems
[patent_app_type] => utility
[patent_app_number] => 17/321708
[patent_app_country] => US
[patent_app_date] => 2021-05-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 5234
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 171
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17321708
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/321708 | Power reduction in very large-scale integration (VLSI) systems | May 16, 2021 | Issued |
Array
(
[id] => 18547385
[patent_doc_number] => 11720738
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-08-08
[patent_title] => Leakage analysis on semiconductor device
[patent_app_type] => utility
[patent_app_number] => 17/315023
[patent_app_country] => US
[patent_app_date] => 2021-05-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 18
[patent_no_of_words] => 10925
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 161
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17315023
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/315023 | Leakage analysis on semiconductor device | May 6, 2021 | Issued |
Array
(
[id] => 18357038
[patent_doc_number] => 11645442
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2023-05-09
[patent_title] => Method for reducing cost and increasing accuracy of variational quantum circuit optimization
[patent_app_type] => utility
[patent_app_number] => 17/238977
[patent_app_country] => US
[patent_app_date] => 2021-04-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 11
[patent_no_of_words] => 6296
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 154
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17238977
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/238977 | Method for reducing cost and increasing accuracy of variational quantum circuit optimization | Apr 22, 2021 | Issued |
Array
(
[id] => 18291560
[patent_doc_number] => 11620430
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-04-04
[patent_title] => Autoplacement of superconducting devices
[patent_app_type] => utility
[patent_app_number] => 17/235772
[patent_app_country] => US
[patent_app_date] => 2021-04-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 11
[patent_no_of_words] => 7086
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 150
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17235772
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/235772 | Autoplacement of superconducting devices | Apr 19, 2021 | Issued |
Array
(
[id] => 18291560
[patent_doc_number] => 11620430
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-04-04
[patent_title] => Autoplacement of superconducting devices
[patent_app_type] => utility
[patent_app_number] => 17/235772
[patent_app_country] => US
[patent_app_date] => 2021-04-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 11
[patent_no_of_words] => 7086
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 150
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17235772
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/235772 | Autoplacement of superconducting devices | Apr 19, 2021 | Issued |
Array
(
[id] => 18291560
[patent_doc_number] => 11620430
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-04-04
[patent_title] => Autoplacement of superconducting devices
[patent_app_type] => utility
[patent_app_number] => 17/235772
[patent_app_country] => US
[patent_app_date] => 2021-04-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 11
[patent_no_of_words] => 7086
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 150
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17235772
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/235772 | Autoplacement of superconducting devices | Apr 19, 2021 | Issued |
Array
(
[id] => 18291560
[patent_doc_number] => 11620430
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-04-04
[patent_title] => Autoplacement of superconducting devices
[patent_app_type] => utility
[patent_app_number] => 17/235772
[patent_app_country] => US
[patent_app_date] => 2021-04-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 11
[patent_no_of_words] => 7086
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 150
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17235772
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/235772 | Autoplacement of superconducting devices | Apr 19, 2021 | Issued |
Array
(
[id] => 17948167
[patent_doc_number] => 20220335186
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-10-20
[patent_title] => METHOD FOR AUTOMATIC PROCESSOR DESIGN, VALIDATION, AND VERIFICATION
[patent_app_type] => utility
[patent_app_number] => 17/230898
[patent_app_country] => US
[patent_app_date] => 2021-04-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7236
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 68
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17230898
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/230898 | Method for automatic processor design, validation, and verification | Apr 13, 2021 | Issued |
Array
(
[id] => 18401254
[patent_doc_number] => 11663392
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-05-30
[patent_title] => Timing driven cell swapping
[patent_app_type] => utility
[patent_app_number] => 17/227462
[patent_app_country] => US
[patent_app_date] => 2021-04-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4791
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 73
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17227462
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/227462 | Timing driven cell swapping | Apr 11, 2021 | Issued |
Array
(
[id] => 18415121
[patent_doc_number] => 11669664
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-06-06
[patent_title] => System on chip (SOC) current profile model for integrated voltage regulator (IVR) co-design
[patent_app_type] => utility
[patent_app_number] => 17/222108
[patent_app_country] => US
[patent_app_date] => 2021-04-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 5590
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17222108
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/222108 | System on chip (SOC) current profile model for integrated voltage regulator (IVR) co-design | Apr 4, 2021 | Issued |
Array
(
[id] => 17916084
[patent_doc_number] => 20220318480
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-10-06
[patent_title] => PRUNING REDUNDANT BUFFERING SOLUTIONS USING FAST TIMING MODELS
[patent_app_type] => utility
[patent_app_number] => 17/219748
[patent_app_country] => US
[patent_app_date] => 2021-03-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6553
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 177
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17219748
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/219748 | Pruning redundant buffering solutions using fast timing models | Mar 30, 2021 | Issued |
Array
(
[id] => 18174389
[patent_doc_number] => 11574101
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-02-07
[patent_title] => Techniques for providing optimizations based on categories of slack in timing paths
[patent_app_type] => utility
[patent_app_number] => 17/213021
[patent_app_country] => US
[patent_app_date] => 2021-03-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 12
[patent_no_of_words] => 11424
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 140
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17213021
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/213021 | Techniques for providing optimizations based on categories of slack in timing paths | Mar 24, 2021 | Issued |
Array
(
[id] => 19538550
[patent_doc_number] => 12131103
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-10-29
[patent_title] => Semiconductor fabrication process parameter determination using a generative adversarial network
[patent_app_type] => utility
[patent_app_number] => 17/211011
[patent_app_country] => US
[patent_app_date] => 2021-03-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 5398
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 96
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17211011
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/211011 | Semiconductor fabrication process parameter determination using a generative adversarial network | Mar 23, 2021 | Issued |
Array
(
[id] => 18014675
[patent_doc_number] => 11506970
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-11-22
[patent_title] => Method of forming photomask
[patent_app_type] => utility
[patent_app_number] => 17/210469
[patent_app_country] => US
[patent_app_date] => 2021-03-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 14
[patent_no_of_words] => 5732
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 256
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17210469
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/210469 | Method of forming photomask | Mar 22, 2021 | Issued |
Array
(
[id] => 18687366
[patent_doc_number] => 11783105
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-10-10
[patent_title] => Method and system for verifying a sorter
[patent_app_type] => utility
[patent_app_number] => 17/207030
[patent_app_country] => US
[patent_app_date] => 2021-03-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 12
[patent_no_of_words] => 12087
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 91
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17207030
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/207030 | Method and system for verifying a sorter | Mar 18, 2021 | Issued |
Array
(
[id] => 18155137
[patent_doc_number] => 11568117
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-01-31
[patent_title] => Generating simulation-friendly compact physical models for passive structures
[patent_app_type] => utility
[patent_app_number] => 17/196573
[patent_app_country] => US
[patent_app_date] => 2021-03-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 8327
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 185
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17196573
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/196573 | Generating simulation-friendly compact physical models for passive structures | Mar 8, 2021 | Issued |
Array
(
[id] => 18307548
[patent_doc_number] => 20230111448
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-04-13
[patent_title] => ANALOGUE CIRCUIT DESIGN
[patent_app_type] => utility
[patent_app_number] => 17/910616
[patent_app_country] => US
[patent_app_date] => 2021-02-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13802
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -23
[patent_words_short_claim] => 37
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17910616
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/910616 | Analogue circuit design | Feb 21, 2021 | Issued |
Array
(
[id] => 17039551
[patent_doc_number] => 20210256187
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-08-19
[patent_title] => Field Programmable Analog Array
[patent_app_type] => utility
[patent_app_number] => 17/178551
[patent_app_country] => US
[patent_app_date] => 2021-02-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12606
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -39
[patent_words_short_claim] => 92
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17178551
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/178551 | Field programmable analog array | Feb 17, 2021 | Issued |
Array
(
[id] => 18316852
[patent_doc_number] => 11630934
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2023-04-18
[patent_title] => Integrated circuit analysis using a multi-level data hierarchy implemented on a distributed compute and data infrastructure
[patent_app_type] => utility
[patent_app_number] => 17/175268
[patent_app_country] => US
[patent_app_date] => 2021-02-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 6475
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 120
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17175268
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/175268 | Integrated circuit analysis using a multi-level data hierarchy implemented on a distributed compute and data infrastructure | Feb 11, 2021 | Issued |
Array
(
[id] => 17038723
[patent_doc_number] => 20210255682
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-08-19
[patent_title] => BOUNDARY PORT POWER INTENT MODELLING AND MANAGEMENT
[patent_app_type] => utility
[patent_app_number] => 17/156910
[patent_app_country] => US
[patent_app_date] => 2021-01-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4461
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 47
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17156910
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/156910 | Boundary port power in pent modelling and management | Jan 24, 2021 | Issued |