Search

Brandon Bowers

Examiner (ID: 10602, Phone: (571)272-1888 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2825, 2851
Total Applications
889
Issued Applications
747
Pending Applications
56
Abandoned Applications
107

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18014675 [patent_doc_number] => 11506970 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-22 [patent_title] => Method of forming photomask [patent_app_type] => utility [patent_app_number] => 17/210469 [patent_app_country] => US [patent_app_date] => 2021-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 5732 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17210469 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/210469
Method of forming photomask Mar 22, 2021 Issued
Array ( [id] => 18687366 [patent_doc_number] => 11783105 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-10 [patent_title] => Method and system for verifying a sorter [patent_app_type] => utility [patent_app_number] => 17/207030 [patent_app_country] => US [patent_app_date] => 2021-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 12087 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17207030 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/207030
Method and system for verifying a sorter Mar 18, 2021 Issued
Array ( [id] => 18155137 [patent_doc_number] => 11568117 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-31 [patent_title] => Generating simulation-friendly compact physical models for passive structures [patent_app_type] => utility [patent_app_number] => 17/196573 [patent_app_country] => US [patent_app_date] => 2021-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8327 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17196573 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/196573
Generating simulation-friendly compact physical models for passive structures Mar 8, 2021 Issued
Array ( [id] => 18307548 [patent_doc_number] => 20230111448 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-13 [patent_title] => ANALOGUE CIRCUIT DESIGN [patent_app_type] => utility [patent_app_number] => 17/910616 [patent_app_country] => US [patent_app_date] => 2021-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13802 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17910616 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/910616
Analogue circuit design Feb 21, 2021 Issued
Array ( [id] => 17039551 [patent_doc_number] => 20210256187 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-19 [patent_title] => Field Programmable Analog Array [patent_app_type] => utility [patent_app_number] => 17/178551 [patent_app_country] => US [patent_app_date] => 2021-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12606 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -39 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17178551 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/178551
Field programmable analog array Feb 17, 2021 Issued
Array ( [id] => 18316852 [patent_doc_number] => 11630934 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-04-18 [patent_title] => Integrated circuit analysis using a multi-level data hierarchy implemented on a distributed compute and data infrastructure [patent_app_type] => utility [patent_app_number] => 17/175268 [patent_app_country] => US [patent_app_date] => 2021-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 6475 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17175268 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/175268
Integrated circuit analysis using a multi-level data hierarchy implemented on a distributed compute and data infrastructure Feb 11, 2021 Issued
Array ( [id] => 17038723 [patent_doc_number] => 20210255682 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-19 [patent_title] => BOUNDARY PORT POWER INTENT MODELLING AND MANAGEMENT [patent_app_type] => utility [patent_app_number] => 17/156910 [patent_app_country] => US [patent_app_date] => 2021-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4461 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17156910 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/156910
Boundary port power in pent modelling and management Jan 24, 2021 Issued
Array ( [id] => 17751759 [patent_doc_number] => 20220229964 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-21 [patent_title] => MODULAR PRINTED CIRCUIT BOARD ENCLOSURE [patent_app_type] => utility [patent_app_number] => 17/150622 [patent_app_country] => US [patent_app_date] => 2021-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8541 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17150622 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/150622
Modular printed circuit board enclosure Jan 14, 2021 Issued
Array ( [id] => 18638445 [patent_doc_number] => 11763050 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-09-19 [patent_title] => System, method, and computer program product for augmented reality circuit design [patent_app_type] => utility [patent_app_number] => 17/145960 [patent_app_country] => US [patent_app_date] => 2021-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 10953 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17145960 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/145960
System, method, and computer program product for augmented reality circuit design Jan 10, 2021 Issued
Array ( [id] => 18189693 [patent_doc_number] => 11580284 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-02-14 [patent_title] => System, method, and computer program product for finding and analyzing deadlock conditions associated with the formal verification of an electronic circuit design [patent_app_type] => utility [patent_app_number] => 17/142360 [patent_app_country] => US [patent_app_date] => 2021-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6848 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17142360 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/142360
System, method, and computer program product for finding and analyzing deadlock conditions associated with the formal verification of an electronic circuit design Jan 5, 2021 Issued
Array ( [id] => 16936294 [patent_doc_number] => 20210202183 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-01 [patent_title] => PARALLEL PLATE CAPACITOR RESISTANCE MODELING AND EXTRACTION [patent_app_type] => utility [patent_app_number] => 17/139185 [patent_app_country] => US [patent_app_date] => 2020-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5159 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17139185 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/139185
Parallel plate capacitor resistance modeling and extraction Dec 30, 2020 Issued
Array ( [id] => 17999936 [patent_doc_number] => 11501044 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-11-15 [patent_title] => System and method for decoupling capacitor selection and placement using genetic optimization [patent_app_type] => utility [patent_app_number] => 17/132943 [patent_app_country] => US [patent_app_date] => 2020-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 4994 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17132943 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/132943
System and method for decoupling capacitor selection and placement using genetic optimization Dec 22, 2020 Issued
Array ( [id] => 17528924 [patent_doc_number] => 11301613 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-12 [patent_title] => Systems and methods for performing depth-dependent oxidation modeling and depth-dependent etch modeling in a virtual fabrication environment [patent_app_type] => utility [patent_app_number] => 17/130473 [patent_app_country] => US [patent_app_date] => 2020-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 10913 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17130473 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/130473
Systems and methods for performing depth-dependent oxidation modeling and depth-dependent etch modeling in a virtual fabrication environment Dec 21, 2020 Issued
Array ( [id] => 18276283 [patent_doc_number] => 11615227 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-28 [patent_title] => Method and system for latch-up prevention [patent_app_type] => utility [patent_app_number] => 17/129195 [patent_app_country] => US [patent_app_date] => 2020-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 20 [patent_no_of_words] => 5390 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17129195 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/129195
Method and system for latch-up prevention Dec 20, 2020 Issued
Array ( [id] => 17543133 [patent_doc_number] => 11308257 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-04-19 [patent_title] => Stacked via rivets in chip hotspots [patent_app_type] => utility [patent_app_number] => 17/122550 [patent_app_country] => US [patent_app_date] => 2020-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 18989 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17122550 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/122550
Stacked via rivets in chip hotspots Dec 14, 2020 Issued
Array ( [id] => 17380182 [patent_doc_number] => 11238199 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-02-01 [patent_title] => High-level synthesis vector library for single-instruction multiple data programming and electronic system design [patent_app_type] => utility [patent_app_number] => 17/116720 [patent_app_country] => US [patent_app_date] => 2020-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 12294 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17116720 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/116720
High-level synthesis vector library for single-instruction multiple data programming and electronic system design Dec 8, 2020 Issued
Array ( [id] => 17114354 [patent_doc_number] => 20210294951 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-23 [patent_title] => ELECTRONIC APPARATUS FOR AUTOMATICALLY ARRANGING A PLURALITY OF OBJECTS ON DRAWING, CONTROL METHOD THEREOF AND COMPUTER-READABLE RECORDING MEDIUM THEREOF [patent_app_type] => utility [patent_app_number] => 17/104345 [patent_app_country] => US [patent_app_date] => 2020-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7479 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17104345 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/104345
ELECTRONIC APPARATUS FOR AUTOMATICALLY ARRANGING A PLURALITY OF OBJECTS ON DRAWING, CONTROL METHOD THEREOF AND COMPUTER-READABLE RECORDING MEDIUM THEREOF Nov 24, 2020 Abandoned
Array ( [id] => 18162271 [patent_doc_number] => 20230028864 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-26 [patent_title] => IN-BODY WIRELESS CHARGING SYSTEM [patent_app_type] => utility [patent_app_number] => 17/778645 [patent_app_country] => US [patent_app_date] => 2020-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9780 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17778645 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/778645
In-body wireless charging system Nov 11, 2020 Issued
Array ( [id] => 18162470 [patent_doc_number] => 20230029063 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-26 [patent_title] => INTEGRATED PHOTONIC DEVICE COMPRISING A FIELD-PROGRAMMABLE PHOTONIC GATE ARRAY, A QUANTUM DEVICE AND PROGRAMMABLE CIRCUITS [patent_app_type] => utility [patent_app_number] => 17/785294 [patent_app_country] => US [patent_app_date] => 2020-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3562 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17785294 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/785294
INTEGRATED PHOTONIC DEVICE COMPRISING A FIELD-PROGRAMMABLE PHOTONIC GATE ARRAY, A QUANTUM DEVICE AND PROGRAMMABLE CIRCUITS Oct 29, 2020 Pending
Array ( [id] => 17507841 [patent_doc_number] => 20220100944 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-31 [patent_title] => METHOD FOR DESIGNING POWER NETWORK AND POWER NETWORK [patent_app_type] => utility [patent_app_number] => 17/085059 [patent_app_country] => US [patent_app_date] => 2020-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6202 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17085059 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/085059
Method for designing power network and power network Oct 29, 2020 Issued
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