Search

Brandon Bowers

Examiner (ID: 10602, Phone: (571)272-1888 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2825, 2851
Total Applications
889
Issued Applications
747
Pending Applications
56
Abandoned Applications
107

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17564750 [patent_doc_number] => 20220128899 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-28 [patent_title] => METHODS AND SYSTEMS TO DETERMINE SHAPES FOR SEMICONDUCTOR OR FLAT PANEL DISPLAY FABRICATION [patent_app_type] => utility [patent_app_number] => 16/949270 [patent_app_country] => US [patent_app_date] => 2020-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16225 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16949270 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/949270
Methods and systems to determine shapes for semiconductor or flat panel display fabrication Oct 21, 2020 Issued
Array ( [id] => 17564750 [patent_doc_number] => 20220128899 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-28 [patent_title] => METHODS AND SYSTEMS TO DETERMINE SHAPES FOR SEMICONDUCTOR OR FLAT PANEL DISPLAY FABRICATION [patent_app_type] => utility [patent_app_number] => 16/949270 [patent_app_country] => US [patent_app_date] => 2020-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16225 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16949270 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/949270
Methods and systems to determine shapes for semiconductor or flat panel display fabrication Oct 21, 2020 Issued
Array ( [id] => 18734948 [patent_doc_number] => 11803682 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-31 [patent_title] => Semiconductor device including standard cell having split portions [patent_app_type] => utility [patent_app_number] => 17/072792 [patent_app_country] => US [patent_app_date] => 2020-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 13674 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17072792 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/072792
Semiconductor device including standard cell having split portions Oct 15, 2020 Issued
Array ( [id] => 19792818 [patent_doc_number] => 12233745 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-25 [patent_title] => Estimation device, estimation method, and computer program [patent_app_type] => utility [patent_app_number] => 17/765223 [patent_app_country] => US [patent_app_date] => 2020-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 12036 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17765223 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/765223
Estimation device, estimation method, and computer program Oct 1, 2020 Issued
Array ( [id] => 18015423 [patent_doc_number] => 11507721 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-22 [patent_title] => Scan chain wirelength optimization using Q-learning based reinforcement learning [patent_app_type] => utility [patent_app_number] => 17/031977 [patent_app_country] => US [patent_app_date] => 2020-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9192 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17031977 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/031977
Scan chain wirelength optimization using Q-learning based reinforcement learning Sep 24, 2020 Issued
Array ( [id] => 19114433 [patent_doc_number] => 20240126183 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-18 [patent_title] => METHOD FOR RULE-BASED RETARGETING OF TARGET PATTERN [patent_app_type] => utility [patent_app_number] => 17/769107 [patent_app_country] => US [patent_app_date] => 2020-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 25319 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17769107 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/769107
Method for rule-based retargeting of target pattern Sep 23, 2020 Issued
Array ( [id] => 19114433 [patent_doc_number] => 20240126183 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-18 [patent_title] => METHOD FOR RULE-BASED RETARGETING OF TARGET PATTERN [patent_app_type] => utility [patent_app_number] => 17/769107 [patent_app_country] => US [patent_app_date] => 2020-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 25319 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17769107 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/769107
Method for rule-based retargeting of target pattern Sep 23, 2020 Issued
Array ( [id] => 18155138 [patent_doc_number] => 11568118 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-31 [patent_title] => Electronic device, method for generating package drawing and computer readable storage medium [patent_app_type] => utility [patent_app_number] => 17/030689 [patent_app_country] => US [patent_app_date] => 2020-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5523 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17030689 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/030689
Electronic device, method for generating package drawing and computer readable storage medium Sep 23, 2020 Issued
Array ( [id] => 16559365 [patent_doc_number] => 20210004514 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-07 [patent_title] => CHIP DESIGN METHOD OF OPTIMIZING CIRCUIT PERFORMANCE ACCORDING TO CHANGE IN PVT OPERATION CONDITIONS [patent_app_type] => utility [patent_app_number] => 17/028172 [patent_app_country] => US [patent_app_date] => 2020-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7092 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17028172 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/028172
Chip design method of optimizing circuit performance according to change in PVT operation conditions Sep 21, 2020 Issued
Array ( [id] => 17409312 [patent_doc_number] => 11250199 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-02-15 [patent_title] => Methods and systems for generating shape data for electronic designs [patent_app_type] => utility [patent_app_number] => 17/022363 [patent_app_country] => US [patent_app_date] => 2020-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5036 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17022363 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/022363
Methods and systems for generating shape data for electronic designs Sep 15, 2020 Issued
Array ( [id] => 17476213 [patent_doc_number] => 20220083717 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-17 [patent_title] => Attribute-Point-Based Timing Constraint Formal Verification [patent_app_type] => utility [patent_app_number] => 17/020948 [patent_app_country] => US [patent_app_date] => 2020-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5600 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17020948 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/020948
Attribute-point-based timing constraint formal verification Sep 14, 2020 Issued
Array ( [id] => 17991365 [patent_doc_number] => 20220357402 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-10 [patent_title] => BATTERY CHARACTERISATION AND MONITORING SYSTEM [patent_app_type] => utility [patent_app_number] => 17/640641 [patent_app_country] => US [patent_app_date] => 2020-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6167 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17640641 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/640641
BATTERY CHARACTERISATION AND MONITORING SYSTEM Sep 3, 2020 Pending
Array ( [id] => 17283331 [patent_doc_number] => 11200361 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-12-14 [patent_title] => Scalable model checking in functional verification by integrating user-guided abstraction [patent_app_type] => utility [patent_app_number] => 17/011226 [patent_app_country] => US [patent_app_date] => 2020-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 8022 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17011226 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/011226
Scalable model checking in functional verification by integrating user-guided abstraction Sep 2, 2020 Issued
Array ( [id] => 18132039 [patent_doc_number] => 11558259 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-17 [patent_title] => System and method for generating and using physical roadmaps in network synthesis [patent_app_type] => utility [patent_app_number] => 17/002186 [patent_app_country] => US [patent_app_date] => 2020-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 20 [patent_no_of_words] => 7144 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17002186 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/002186
System and method for generating and using physical roadmaps in network synthesis Aug 24, 2020 Issued
Array ( [id] => 19764367 [patent_doc_number] => 12222656 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-11 [patent_title] => Method for determining aberration sensitivity of patterns [patent_app_type] => utility [patent_app_number] => 17/638899 [patent_app_country] => US [patent_app_date] => 2020-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 28 [patent_no_of_words] => 19142 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17638899 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/638899
Method for determining aberration sensitivity of patterns Aug 20, 2020 Issued
Array ( [id] => 17409308 [patent_doc_number] => 11250195 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-15 [patent_title] => Method and system for ROM based dynamic thermal management analysis and control [patent_app_type] => utility [patent_app_number] => 16/947756 [patent_app_country] => US [patent_app_date] => 2020-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 19 [patent_no_of_words] => 7436 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16947756 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/947756
Method and system for ROM based dynamic thermal management analysis and control Aug 13, 2020 Issued
Array ( [id] => 17416046 [patent_doc_number] => 20220050950 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-17 [patent_title] => SEMICONDUCTOR DEVICE INCLUDING REGIONS FOR REDUCING DENSITY GRADIENT EFFECT AND METHOD OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 16/991929 [patent_app_country] => US [patent_app_date] => 2020-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13500 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16991929 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/991929
Semiconductor device including regions for reducing density gradient effect and method of forming the same Aug 11, 2020 Issued
Array ( [id] => 17786811 [patent_doc_number] => 11409936 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-09 [patent_title] => Standard cell establishment method [patent_app_type] => utility [patent_app_number] => 16/990992 [patent_app_country] => US [patent_app_date] => 2020-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1756 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16990992 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/990992
Standard cell establishment method Aug 10, 2020 Issued
Array ( [id] => 16543735 [patent_doc_number] => 20200410150 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-31 [patent_title] => GENERATING A TEMPLATE-DRIVEN SCHEMATIC FROM A NETLIST OF ELECTRONIC CIRCUITS [patent_app_type] => utility [patent_app_number] => 16/983374 [patent_app_country] => US [patent_app_date] => 2020-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6972 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16983374 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/983374
Generating a template-driven schematic from a netlist of electronic circuits Aug 2, 2020 Issued
Array ( [id] => 18415126 [patent_doc_number] => 11669669 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-06 [patent_title] => Circuit layouts and related methods [patent_app_type] => utility [patent_app_number] => 16/943827 [patent_app_country] => US [patent_app_date] => 2020-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 8209 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16943827 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/943827
Circuit layouts and related methods Jul 29, 2020 Issued
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