Search

Brandon S. Cole

Examiner (ID: 5829, Phone: (571)270-5075 , Office: P/2842 )

Most Active Art Unit
2842
Art Unit(s)
2842, 2128, 2816, 2122
Total Applications
1478
Issued Applications
1171
Pending Applications
78
Abandoned Applications
254

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19749180 [patent_doc_number] => 20250037745 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-30 [patent_title] => MEMORY READOUT CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/782285 [patent_app_country] => US [patent_app_date] => 2024-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4637 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18782285 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/782285
MEMORY READOUT CIRCUIT Jul 23, 2024 Pending
Array ( [id] => 19714619 [patent_doc_number] => 20250024761 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-16 [patent_title] => RANDOM NUMBER GENERATION BASED ON THRESHOLD VOLTAGE RANDOMNESS [patent_app_type] => utility [patent_app_number] => 18/782436 [patent_app_country] => US [patent_app_date] => 2024-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17147 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18782436 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/782436
RANDOM NUMBER GENERATION BASED ON THRESHOLD VOLTAGE RANDOMNESS Jul 23, 2024 Pending
Array ( [id] => 19912377 [patent_doc_number] => 12288595 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-29 [patent_title] => System and method for providing compression attached memory module compression connectors [patent_app_type] => utility [patent_app_number] => 18/775312 [patent_app_country] => US [patent_app_date] => 2024-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 5998 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18775312 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/775312
System and method for providing compression attached memory module compression connectors Jul 16, 2024 Issued
Array ( [id] => 19546154 [patent_doc_number] => 20240363190 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-31 [patent_title] => ADAPTIVE ERROR AVOIDANCE IN THE MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 18/771393 [patent_app_country] => US [patent_app_date] => 2024-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10012 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18771393 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/771393
ADAPTIVE ERROR AVOIDANCE IN THE MEMORY DEVICES Jul 11, 2024 Pending
Array ( [id] => 19548520 [patent_doc_number] => 20240365556 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-31 [patent_title] => COMPUTE-IN-MEMORY DEVICE AND METHOD [patent_app_type] => utility [patent_app_number] => 18/769532 [patent_app_country] => US [patent_app_date] => 2024-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4645 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18769532 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/769532
COMPUTE-IN-MEMORY DEVICE AND METHOD Jul 10, 2024 Pending
Array ( [id] => 20088559 [patent_doc_number] => 20250218495 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-03 [patent_title] => MEMORY CORE CIRCUIT HAVING CELL ON PERIPHERY (COP) STRUCTURE AND MEMORY DEVICE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/767238 [patent_app_country] => US [patent_app_date] => 2024-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13079 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18767238 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/767238
MEMORY CORE CIRCUIT HAVING CELL ON PERIPHERY (COP) STRUCTURE AND MEMORY DEVICE INCLUDING THE SAME Jul 8, 2024 Pending
Array ( [id] => 19712350 [patent_doc_number] => 20250022492 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-16 [patent_title] => POWER CONTROL CHAIN [patent_app_type] => utility [patent_app_number] => 18/766414 [patent_app_country] => US [patent_app_date] => 2024-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12690 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18766414 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/766414
POWER CONTROL CHAIN Jul 7, 2024 Pending
Array ( [id] => 20167611 [patent_doc_number] => 20250259658 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-14 [patent_title] => POWER SUPPLY CIRCUIT, SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 18/749616 [patent_app_country] => US [patent_app_date] => 2024-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8770 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18749616 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/749616
POWER SUPPLY CIRCUIT, SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE Jun 20, 2024 Pending
Array ( [id] => 20381559 [patent_doc_number] => 20250364052 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-11-27 [patent_title] => PROGRAM OPERATIONS IN MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 18/749538 [patent_app_country] => US [patent_app_date] => 2024-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9111 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 274 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18749538 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/749538
PROGRAM OPERATIONS IN MEMORY DEVICES Jun 19, 2024 Pending
Array ( [id] => 19712707 [patent_doc_number] => 20250022849 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-16 [patent_title] => VERTICALLY INTEGRATED MEMORY SYSTEM AND ASSOCIATED SYSTEMS AND METHODS [patent_app_type] => utility [patent_app_number] => 18/749416 [patent_app_country] => US [patent_app_date] => 2024-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11326 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18749416 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/749416
VERTICALLY INTEGRATED MEMORY SYSTEM AND ASSOCIATED SYSTEMS AND METHODS Jun 19, 2024 Pending
Array ( [id] => 20175716 [patent_doc_number] => 12394469 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-19 [patent_title] => DRAM computation circuit and method [patent_app_type] => utility [patent_app_number] => 18/743950 [patent_app_country] => US [patent_app_date] => 2024-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 6557 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18743950 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/743950
DRAM computation circuit and method Jun 13, 2024 Issued
Array ( [id] => 19483724 [patent_doc_number] => 20240331766 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => SRAM Design with Four-Poly-Pitch [patent_app_type] => utility [patent_app_number] => 18/744280 [patent_app_country] => US [patent_app_date] => 2024-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14286 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18744280 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/744280
SRAM design with four-poly-pitch Jun 13, 2024 Issued
Array ( [id] => 20596288 [patent_doc_number] => 12580011 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-17 [patent_title] => Memory circuit and method of operating same [patent_app_type] => utility [patent_app_number] => 18/739767 [patent_app_country] => US [patent_app_date] => 2024-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 11328 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18739767 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/739767
Memory circuit and method of operating same Jun 10, 2024 Issued
Array ( [id] => 19618918 [patent_doc_number] => 20240404598 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-05 [patent_title] => 3D CELL AND ARRAY STRUCTURES [patent_app_type] => utility [patent_app_number] => 18/735147 [patent_app_country] => US [patent_app_date] => 2024-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 34386 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18735147 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/735147
3D CELL AND ARRAY STRUCTURES Jun 4, 2024 Pending
Array ( [id] => 19646240 [patent_doc_number] => 20240420760 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-19 [patent_title] => MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/669285 [patent_app_country] => US [patent_app_date] => 2024-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7424 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18669285 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/669285
MEMORY DEVICE May 19, 2024 Pending
Array ( [id] => 19420773 [patent_doc_number] => 20240296897 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-05 [patent_title] => TECHNIQUES FOR DETERMINING AN INTERFACE CONNECTION STATUS [patent_app_type] => utility [patent_app_number] => 18/660002 [patent_app_country] => US [patent_app_date] => 2024-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16251 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18660002 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/660002
Techniques for determining an interface connection status May 8, 2024 Issued
Array ( [id] => 19406873 [patent_doc_number] => 20240290384 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-29 [patent_title] => ACCESS COMMAND DELAY USING COMMAND DELAY CIRCUITRY [patent_app_type] => utility [patent_app_number] => 18/658559 [patent_app_country] => US [patent_app_date] => 2024-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7953 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18658559 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/658559
Access command delay using command delay circuitry May 7, 2024 Issued
Array ( [id] => 19406861 [patent_doc_number] => 20240290372 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-29 [patent_title] => DOUBLE DATA RATE (DDR) MEMORY CONTROLLER APPARATUS AND METHOD [patent_app_type] => utility [patent_app_number] => 18/657640 [patent_app_country] => US [patent_app_date] => 2024-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9598 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18657640 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/657640
DOUBLE DATA RATE (DDR) MEMORY CONTROLLER APPARATUS AND METHOD May 6, 2024 Abandoned
Array ( [id] => 19394798 [patent_doc_number] => 20240284668 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-22 [patent_title] => MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 18/653241 [patent_app_country] => US [patent_app_date] => 2024-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 27324 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18653241 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/653241
Memory system May 1, 2024 Issued
Array ( [id] => 20332576 [patent_doc_number] => 12462860 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-04 [patent_title] => Using split word lines and switches for reducing capacitive loading on a memory system [patent_app_type] => utility [patent_app_number] => 18/647743 [patent_app_country] => US [patent_app_date] => 2024-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 23 [patent_no_of_words] => 7156 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18647743 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/647743
Using split word lines and switches for reducing capacitive loading on a memory system Apr 25, 2024 Issued
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