
Brandon S. Cole
Examiner (ID: 2216, Phone: (571)270-5075 , Office: P/2842 )
| Most Active Art Unit | 2842 |
| Art Unit(s) | 2122, 2128, 2816, 2842 |
| Total Applications | 1460 |
| Issued Applications | 1165 |
| Pending Applications | 80 |
| Abandoned Applications | 249 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 10224045
[patent_doc_number] => 20150109038
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-04-23
[patent_title] => 'System Clock Jitter Correction'
[patent_app_type] => utility
[patent_app_number] => 14/562914
[patent_app_country] => US
[patent_app_date] => 2014-12-08
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Array
(
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[patent_doc_number] => 20160110650
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[patent_kind] => A1
[patent_issue_date] => 2016-04-21
[patent_title] => 'ADVANCED CONTEXT-BASED DRIVER SCORING'
[patent_app_type] => utility
[patent_app_number] => 14/556726
[patent_app_country] => US
[patent_app_date] => 2014-12-01
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Array
(
[id] => 10803407
[patent_doc_number] => 20160149564
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-05-26
[patent_title] => 'DELAY LINE CIRCUIT'
[patent_app_type] => utility
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[patent_app_country] => US
[patent_app_date] => 2014-11-26
[patent_effective_date] => 0000-00-00
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Array
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[id] => 10159210
[patent_doc_number] => 09190995
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[patent_kind] => B2
[patent_issue_date] => 2015-11-17
[patent_title] => 'Multiple power domain electronic device and related method'
[patent_app_type] => utility
[patent_app_number] => 14/547628
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Array
(
[id] => 10231008
[patent_doc_number] => 20150116002
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[patent_kind] => A1
[patent_issue_date] => 2015-04-30
[patent_title] => 'SEMICONDUCTOR APPARATUS'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/541912 | SEMICONDUCTOR APPARATUS | Nov 13, 2014 | Abandoned |
Array
(
[id] => 11227975
[patent_doc_number] => 09455703
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[patent_issue_date] => 2016-09-27
[patent_title] => 'FET array bypass module'
[patent_app_type] => utility
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Array
(
[id] => 11104439
[patent_doc_number] => 20160301409
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[patent_title] => 'ASYMMETRIC GATE DRIVER APPARATUS, METHODS, AND SYSTEMS'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/781448 | Asymmetric gate driver apparatus, methods, and systems | Nov 10, 2014 | Issued |
Array
(
[id] => 11896342
[patent_doc_number] => 09766274
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[patent_issue_date] => 2017-09-19
[patent_title] => 'Current sampling circuit and method'
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Array
(
[id] => 14399205
[patent_doc_number] => 10312897
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[patent_kind] => B2
[patent_issue_date] => 2019-06-04
[patent_title] => Switching device
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[patent_app_number] => 15/039612
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Array
(
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Array
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Array
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Array
(
[id] => 11036801
[patent_doc_number] => 20160233757
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[patent_title] => 'LOW LEVEL HARMONICS CONTROL SYSTEM FOR GROUPS OF IMPEDANCES CONNECTED IN PARALLEL IN A THREE-PHASE SYSTEM'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/021838 | LOW LEVEL HARMONICS CONTROL SYSTEM FOR GROUPS OF IMPEDANCES CONNECTED IN PARALLEL IN A THREE-PHASE SYSTEM | Oct 27, 2014 | Abandoned |
Array
(
[id] => 10710648
[patent_doc_number] => 20160056796
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[patent_issue_date] => 2016-02-25
[patent_title] => 'INTEGRATED CIRCUITS'
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/031115 | Dual-loop programmable and dividerless clock generator for ultra low power applications | Oct 21, 2014 | Issued |
Array
(
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Array
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