Search

Brandon S. Cole

Examiner (ID: 2216, Phone: (571)270-5075 , Office: P/2842 )

Most Active Art Unit
2842
Art Unit(s)
2122, 2128, 2816, 2842
Total Applications
1460
Issued Applications
1165
Pending Applications
80
Abandoned Applications
249

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10224045 [patent_doc_number] => 20150109038 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-23 [patent_title] => 'System Clock Jitter Correction' [patent_app_type] => utility [patent_app_number] => 14/562914 [patent_app_country] => US [patent_app_date] => 2014-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 7582 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14562914 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/562914
Frequency multiplier jitter correction Dec 7, 2014 Issued
Array ( [id] => 10764495 [patent_doc_number] => 20160110650 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-04-21 [patent_title] => 'ADVANCED CONTEXT-BASED DRIVER SCORING' [patent_app_type] => utility [patent_app_number] => 14/556726 [patent_app_country] => US [patent_app_date] => 2014-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4295 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14556726 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/556726
ADVANCED CONTEXT-BASED DRIVER SCORING Nov 30, 2014 Pending
Array ( [id] => 10803407 [patent_doc_number] => 20160149564 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-26 [patent_title] => 'DELAY LINE CIRCUIT' [patent_app_type] => utility [patent_app_number] => 14/555198 [patent_app_country] => US [patent_app_date] => 2014-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7056 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14555198 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/555198
Delay line circuit Nov 25, 2014 Issued
Array ( [id] => 10159210 [patent_doc_number] => 09190995 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-11-17 [patent_title] => 'Multiple power domain electronic device and related method' [patent_app_type] => utility [patent_app_number] => 14/547628 [patent_app_country] => US [patent_app_date] => 2014-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 8762 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14547628 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/547628
Multiple power domain electronic device and related method Nov 18, 2014 Issued
Array ( [id] => 10231008 [patent_doc_number] => 20150116002 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-30 [patent_title] => 'SEMICONDUCTOR APPARATUS' [patent_app_type] => utility [patent_app_number] => 14/541912 [patent_app_country] => US [patent_app_date] => 2014-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9551 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14541912 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/541912
SEMICONDUCTOR APPARATUS Nov 13, 2014 Abandoned
Array ( [id] => 11227975 [patent_doc_number] => 09455703 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-09-27 [patent_title] => 'FET array bypass module' [patent_app_type] => utility [patent_app_number] => 14/538196 [patent_app_country] => US [patent_app_date] => 2014-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5223 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14538196 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/538196
FET array bypass module Nov 10, 2014 Issued
Array ( [id] => 11104439 [patent_doc_number] => 20160301409 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-13 [patent_title] => 'ASYMMETRIC GATE DRIVER APPARATUS, METHODS, AND SYSTEMS' [patent_app_type] => utility [patent_app_number] => 14/781448 [patent_app_country] => US [patent_app_date] => 2014-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5966 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14781448 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/781448
Asymmetric gate driver apparatus, methods, and systems Nov 10, 2014 Issued
Array ( [id] => 11896342 [patent_doc_number] => 09766274 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-09-19 [patent_title] => 'Current sampling circuit and method' [patent_app_type] => utility [patent_app_number] => 14/773758 [patent_app_country] => US [patent_app_date] => 2014-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 6056 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14773758 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/773758
Current sampling circuit and method Nov 9, 2014 Issued
Array ( [id] => 14399205 [patent_doc_number] => 10312897 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-04 [patent_title] => Switching device [patent_app_type] => utility [patent_app_number] => 15/039612 [patent_app_country] => US [patent_app_date] => 2014-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 4913 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15039612 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/039612
Switching device Nov 5, 2014 Issued
Array ( [id] => 11740051 [patent_doc_number] => 09704644 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-07-11 [patent_title] => 'Flexible circuit assembly and method therof' [patent_app_type] => utility [patent_app_number] => 14/531079 [patent_app_country] => US [patent_app_date] => 2014-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 24 [patent_no_of_words] => 7298 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14531079 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/531079
Flexible circuit assembly and method therof Nov 2, 2014 Issued
Array ( [id] => 11740051 [patent_doc_number] => 09704644 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-07-11 [patent_title] => 'Flexible circuit assembly and method therof' [patent_app_type] => utility [patent_app_number] => 14/531079 [patent_app_country] => US [patent_app_date] => 2014-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 24 [patent_no_of_words] => 7298 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14531079 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/531079
Flexible circuit assembly and method therof Nov 2, 2014 Issued
Array ( [id] => 11740051 [patent_doc_number] => 09704644 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-07-11 [patent_title] => 'Flexible circuit assembly and method therof' [patent_app_type] => utility [patent_app_number] => 14/531079 [patent_app_country] => US [patent_app_date] => 2014-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 24 [patent_no_of_words] => 7298 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14531079 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/531079
Flexible circuit assembly and method therof Nov 2, 2014 Issued
Array ( [id] => 11740051 [patent_doc_number] => 09704644 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-07-11 [patent_title] => 'Flexible circuit assembly and method therof' [patent_app_type] => utility [patent_app_number] => 14/531079 [patent_app_country] => US [patent_app_date] => 2014-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 24 [patent_no_of_words] => 7298 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14531079 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/531079
Flexible circuit assembly and method therof Nov 2, 2014 Issued
Array ( [id] => 11036801 [patent_doc_number] => 20160233757 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-11 [patent_title] => 'LOW LEVEL HARMONICS CONTROL SYSTEM FOR GROUPS OF IMPEDANCES CONNECTED IN PARALLEL IN A THREE-PHASE SYSTEM' [patent_app_type] => utility [patent_app_number] => 15/021838 [patent_app_country] => US [patent_app_date] => 2014-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2898 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15021838 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/021838
LOW LEVEL HARMONICS CONTROL SYSTEM FOR GROUPS OF IMPEDANCES CONNECTED IN PARALLEL IN A THREE-PHASE SYSTEM Oct 27, 2014 Abandoned
Array ( [id] => 10710648 [patent_doc_number] => 20160056796 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-25 [patent_title] => 'INTEGRATED CIRCUITS' [patent_app_type] => utility [patent_app_number] => 14/522764 [patent_app_country] => US [patent_app_date] => 2014-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9681 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14522764 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/522764
INTEGRATED CIRCUITS Oct 23, 2014 Abandoned
Array ( [id] => 11072071 [patent_doc_number] => 20160269035 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-15 [patent_title] => 'DUAL-LOOP PROGRAMMABLE AND DIVIDERLESS CLOCK GENERATOR FOR ULTRA LOW POWER APPLICATIONS' [patent_app_type] => utility [patent_app_number] => 15/031115 [patent_app_country] => US [patent_app_date] => 2014-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3283 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15031115 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/031115
Dual-loop programmable and dividerless clock generator for ultra low power applications Oct 21, 2014 Issued
Array ( [id] => 11788153 [patent_doc_number] => 09397647 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-07-19 [patent_title] => 'Clock spurs reduction technique' [patent_app_type] => utility [patent_app_number] => 14/519671 [patent_app_country] => US [patent_app_date] => 2014-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4794 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14519671 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/519671
Clock spurs reduction technique Oct 20, 2014 Issued
Array ( [id] => 11049361 [patent_doc_number] => 20160246320 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-25 [patent_title] => 'ENERGY SUPPLY CIRCUIT WITHOUT POWER CONVERTER AND ELECTRONIC DEVICE USING SAME' [patent_app_type] => utility [patent_app_number] => 15/030777 [patent_app_country] => US [patent_app_date] => 2014-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4467 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15030777 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/030777
Energy supply circuit without power converter and electronic device using same Oct 20, 2014 Issued
Array ( [id] => 10893509 [patent_doc_number] => 08917125 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-12-23 [patent_title] => 'Interleaving analog-to-digital converter (ADC) with background calibration' [patent_app_type] => utility [patent_app_number] => 14/511206 [patent_app_country] => US [patent_app_date] => 2014-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 6808 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14511206 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/511206
Interleaving analog-to-digital converter (ADC) with background calibration Oct 9, 2014 Issued
Array ( [id] => 9803368 [patent_doc_number] => 20150015313 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-15 [patent_title] => 'FREQUENCY MULTIPLIER JITTER CORRECTION' [patent_app_type] => utility [patent_app_number] => 14/503656 [patent_app_country] => US [patent_app_date] => 2014-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 7516 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14503656 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/503656
Frequency multiplier jitter correction Sep 30, 2014 Issued
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