Search

Brandon S. Cole

Examiner (ID: 2216, Phone: (571)270-5075 , Office: P/2842 )

Most Active Art Unit
2842
Art Unit(s)
2122, 2128, 2816, 2842
Total Applications
1460
Issued Applications
1165
Pending Applications
80
Abandoned Applications
249

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6068442 [patent_doc_number] => 20110043291 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-02-24 [patent_title] => 'DYNAMIC LIMITERS FOR FREQUENCY DIVIDERS' [patent_app_type] => utility [patent_app_number] => 12/633681 [patent_app_country] => US [patent_app_date] => 2009-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5702 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0043/20110043291.pdf [firstpage_image] =>[orig_patent_app_number] => 12633681 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/633681
Dynamic limiters for frequency dividers Dec 7, 2009 Issued
Array ( [id] => 6209152 [patent_doc_number] => 20110133799 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-09 [patent_title] => 'CONFIGURABLE DIGITAL-ANALOG PHASE LOCKED LOOP' [patent_app_type] => utility [patent_app_number] => 12/632061 [patent_app_country] => US [patent_app_date] => 2009-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6298 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0133/20110133799.pdf [firstpage_image] =>[orig_patent_app_number] => 12632061 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/632061
Configurable digital-analog phase locked loop Dec 6, 2009 Issued
Array ( [id] => 7968539 [patent_doc_number] => 07940099 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-10 [patent_title] => 'Method of improving noise characteristics of an ADPLL and a relative ADPLL' [patent_app_type] => utility [patent_app_number] => 12/630585 [patent_app_country] => US [patent_app_date] => 2009-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 3662 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/940/07940099.pdf [firstpage_image] =>[orig_patent_app_number] => 12630585 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/630585
Method of improving noise characteristics of an ADPLL and a relative ADPLL Dec 2, 2009 Issued
Array ( [id] => 6522411 [patent_doc_number] => 20100123512 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-20 [patent_title] => 'Booster circuit' [patent_app_type] => utility [patent_app_number] => 12/590950 [patent_app_country] => US [patent_app_date] => 2009-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1984 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0123/20100123512.pdf [firstpage_image] =>[orig_patent_app_number] => 12590950 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/590950
Booster circuit Nov 16, 2009 Abandoned
Array ( [id] => 8329376 [patent_doc_number] => 08237473 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-08-07 [patent_title] => 'Semiconductor integrated circuit device having plural delay paths and controller capable of blocking signal transmission in delay path' [patent_app_type] => utility [patent_app_number] => 12/588993 [patent_app_country] => US [patent_app_date] => 2009-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 8237 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12588993 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/588993
Semiconductor integrated circuit device having plural delay paths and controller capable of blocking signal transmission in delay path Nov 3, 2009 Issued
Array ( [id] => 5941452 [patent_doc_number] => 20110102072 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-05 [patent_title] => 'Power management of an integrated circuit' [patent_app_type] => utility [patent_app_number] => 12/591017 [patent_app_country] => US [patent_app_date] => 2009-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3994 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0102/20110102072.pdf [firstpage_image] =>[orig_patent_app_number] => 12591017 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/591017
Power management of an integrated circuit Nov 3, 2009 Abandoned
Array ( [id] => 6146277 [patent_doc_number] => 20110018613 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-01-27 [patent_title] => 'SYSTEM AND METHOD FOR PRE-CHARGING A BOOT CAPACITOR IN A SWITCHING REGULATOR WITH HIGH PRE-BIAS VOLTAGE' [patent_app_type] => utility [patent_app_number] => 12/611701 [patent_app_country] => US [patent_app_date] => 2009-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3213 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0018/20110018613.pdf [firstpage_image] =>[orig_patent_app_number] => 12611701 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/611701
System and method for pre-charging a bootstrap capacitor in a switching regulator with high pre-bias voltage Nov 2, 2009 Issued
Array ( [id] => 5941467 [patent_doc_number] => 20110102087 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-05 [patent_title] => 'DC SLOPE GENERATOR' [patent_app_type] => utility [patent_app_number] => 12/610346 [patent_app_country] => US [patent_app_date] => 2009-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1204 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0102/20110102087.pdf [firstpage_image] =>[orig_patent_app_number] => 12610346 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/610346
DC slope generator Nov 1, 2009 Issued
Array ( [id] => 8592735 [patent_doc_number] => 08350612 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-01-08 [patent_title] => 'Circuit for resetting system and delay circuit' [patent_app_type] => utility [patent_app_number] => 12/609381 [patent_app_country] => US [patent_app_date] => 2009-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 5835 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12609381 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/609381
Circuit for resetting system and delay circuit Oct 29, 2009 Issued
Array ( [id] => 6306038 [patent_doc_number] => 20100109719 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-06 [patent_title] => 'PRESCALING STAGE FOR HIGH FREQUENCY APPLICATIONS' [patent_app_type] => utility [patent_app_number] => 12/607655 [patent_app_country] => US [patent_app_date] => 2009-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4464 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0109/20100109719.pdf [firstpage_image] =>[orig_patent_app_number] => 12607655 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/607655
Prescaling stage for high frequency applications Oct 27, 2009 Issued
Array ( [id] => 6452515 [patent_doc_number] => 20100039171 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-18 [patent_title] => 'CURRENT LIMIT CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/606756 [patent_app_country] => US [patent_app_date] => 2009-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6703 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0039/20100039171.pdf [firstpage_image] =>[orig_patent_app_number] => 12606756 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/606756
Current limit circuit and semiconductor memory device Oct 26, 2009 Issued
Array ( [id] => 6021972 [patent_doc_number] => 20110050298 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-03 [patent_title] => 'POWER SUPPLY CIRCUIT FOR SOUTH BRIDGE CHIP' [patent_app_type] => utility [patent_app_number] => 12/605144 [patent_app_country] => US [patent_app_date] => 2009-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1178 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0050/20110050298.pdf [firstpage_image] =>[orig_patent_app_number] => 12605144 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/605144
Power supply circuit for south bridge chip Oct 22, 2009 Issued
Array ( [id] => 7742356 [patent_doc_number] => 08106702 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-01-31 [patent_title] => 'Dynamic enabling pump for power control' [patent_app_type] => utility [patent_app_number] => 12/603572 [patent_app_country] => US [patent_app_date] => 2009-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1559 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/106/08106702.pdf [firstpage_image] =>[orig_patent_app_number] => 12603572 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/603572
Dynamic enabling pump for power control Oct 20, 2009 Issued
Array ( [id] => 8847037 [patent_doc_number] => 08456224 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-06-04 [patent_title] => 'Compensation of operating time-related degradation of operating speed by a constant total die power mode' [patent_app_type] => utility [patent_app_number] => 12/577985 [patent_app_country] => US [patent_app_date] => 2009-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 8040 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12577985 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/577985
Compensation of operating time-related degradation of operating speed by a constant total die power mode Oct 12, 2009 Issued
Array ( [id] => 6344178 [patent_doc_number] => 20100085106 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-08 [patent_title] => 'Method for Operating a Converter Circuit with Voltage Boosting' [patent_app_type] => utility [patent_app_number] => 12/575950 [patent_app_country] => US [patent_app_date] => 2009-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2679 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0085/20100085106.pdf [firstpage_image] =>[orig_patent_app_number] => 12575950 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/575950
Method for operating a converter circuit with voltage boosting Oct 7, 2009 Issued
Array ( [id] => 4434229 [patent_doc_number] => 07969235 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-28 [patent_title] => 'Self-adaptive multi-stage charge pump' [patent_app_type] => utility [patent_app_number] => 12/570646 [patent_app_country] => US [patent_app_date] => 2009-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 5858 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/969/07969235.pdf [firstpage_image] =>[orig_patent_app_number] => 12570646 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/570646
Self-adaptive multi-stage charge pump Sep 29, 2009 Issued
Array ( [id] => 6539282 [patent_doc_number] => 20100271082 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-28 [patent_title] => 'MULTIMODE MILLIMETER-WAVE FREQUENCY DIVIDER CIRCUIT WITH MULTIPLE PRESETTABLE FREQUENCY DIVIDING MODES' [patent_app_type] => utility [patent_app_number] => 12/568828 [patent_app_country] => US [patent_app_date] => 2009-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4084 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0271/20100271082.pdf [firstpage_image] =>[orig_patent_app_number] => 12568828 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/568828
Multimode millimeter-wave frequency divider circuit with multiple presettable frequency dividing modes Sep 28, 2009 Issued
Array ( [id] => 8364403 [patent_doc_number] => 08253469 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-08-28 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/568378 [patent_app_country] => US [patent_app_date] => 2009-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 6350 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12568378 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/568378
Semiconductor device Sep 27, 2009 Issued
Array ( [id] => 7505473 [patent_doc_number] => 08035435 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-10-11 [patent_title] => 'Divided clock synchronization' [patent_app_type] => utility [patent_app_number] => 12/567596 [patent_app_country] => US [patent_app_date] => 2009-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8913 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/035/08035435.pdf [firstpage_image] =>[orig_patent_app_number] => 12567596 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/567596
Divided clock synchronization Sep 24, 2009 Issued
Array ( [id] => 6361796 [patent_doc_number] => 20100079195 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-01 [patent_title] => 'PROTECTED POWER SWITCH WITH LOW CURRENT CONSUMPTION' [patent_app_type] => utility [patent_app_number] => 12/565132 [patent_app_country] => US [patent_app_date] => 2009-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3550 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0079/20100079195.pdf [firstpage_image] =>[orig_patent_app_number] => 12565132 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/565132
Protected power switch with low current consumption Sep 22, 2009 Issued
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