Brandon S. Cole

Array ( [id] => 4451807 [patent_doc_number] => 07965132 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-21 [patent_title] => 'Transistor output circuit and method' [patent_app_type] => utility [patent_app_number] => 12/344120 [patent_app_country] => US [patent_app_date] => 2008-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 5024 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 22 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/965/07965132.pdf [firstpage_image] =>[orig_patent_app_number] => 12344120 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4473233 [patent_doc_number] => 07944278 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-17 [patent_title] => 'Circuit for generating negative voltage and semiconductor memory apparatus using the same' [patent_app_type] => utility [patent_app_number] => 12/343329 [patent_app_country] => US [patent_app_date] => 2008-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3245 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/944/07944278.pdf [firstpage_image] =>[orig_patent_app_number] => 12343329 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5512547 [patent_doc_number] => 20090212851 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-27 [patent_title] => 'POWER SUPPLY UNIT' [patent_app_type] => utility [patent_app_number] => 12/342710 [patent_app_country] => US [patent_app_date] => 2008-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5788 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0212/20090212851.pdf [firstpage_image] =>[orig_patent_app_number] => 12342710 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6404106 [patent_doc_number] => 20100148857 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-17 [patent_title] => 'METHODS AND APPARATUS FOR LOW-VOLTAGE BIAS CURRENT AND BIAS VOLTAGE GENERATION' [patent_app_type] => utility [patent_app_number] => 12/334214 [patent_app_country] => US [patent_app_date] => 2008-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 10900 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20100148857.pdf [firstpage_image] =>[orig_patent_app_number] => 12334214 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5262802 [patent_doc_number] => 20090115487 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-07 [patent_title] => 'Level Converter' [patent_app_type] => utility [patent_app_number] => 12/323694 [patent_app_country] => US [patent_app_date] => 2008-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 12280 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0115/20090115487.pdf [firstpage_image] =>[orig_patent_app_number] => 12323694 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7551351 [patent_doc_number] => 08063686 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-11-22 [patent_title] => 'Phase interpolator circuit with two phase capacitor charging' [patent_app_type] => utility [patent_app_number] => 12/270038 [patent_app_country] => US [patent_app_date] => 2008-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 9329 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/063/08063686.pdf [firstpage_image] =>[orig_patent_app_number] => 12270038 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8551363 [patent_doc_number] => 08326255 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-12-04 [patent_title] => 'Biasing arrangement, electronic apparatus, biasing method, and computer program' [patent_app_type] => utility [patent_app_number] => 12/266988 [patent_app_country] => US [patent_app_date] => 2008-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 17 [patent_no_of_words] => 7661 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12266988 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7685756 [patent_doc_number] => 20100120385 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-13 [patent_title] => 'RADIO FREQUENCY AMPLIFICATION CIRCUIT UTILIZING VARIABLE VOLTAGE GENERATOR' [patent_app_type] => utility [patent_app_number] => 12/267239 [patent_app_country] => US [patent_app_date] => 2008-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2606 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0120/20100120385.pdf [firstpage_image] =>[orig_patent_app_number] => 12267239 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8319084 [patent_doc_number] => 08233875 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-31 [patent_title] => 'Device beacon for handoff management of handoffs to access nodes' [patent_app_type] => utility [patent_app_number] => 12/267261 [patent_app_country] => US [patent_app_date] => 2008-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 26 [patent_no_of_words] => 14792 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12267261 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6306260 [patent_doc_number] => 20100109783 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-06 [patent_title] => 'Reconfigurable Amplifier and Filter Using Time-Varying Circuits' [patent_app_type] => utility [patent_app_number] => 12/263626 [patent_app_country] => US [patent_app_date] => 2008-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5288 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0109/20100109783.pdf [firstpage_image] =>[orig_patent_app_number] => 12263626 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8364385 [patent_doc_number] => 08253454 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-08-28 [patent_title] => 'Phase lock loop with phase interpolation by reference clock and method for the same' [patent_app_type] => utility [patent_app_number] => 12/263456 [patent_app_country] => US [patent_app_date] => 2008-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3792 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12263456 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 54498 [patent_doc_number] => 07772907 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-10 [patent_title] => 'Linear digital phase interpolator and semi-digital delay locked loop (DLL)' [patent_app_type] => utility [patent_app_number] => 12/255170 [patent_app_country] => US [patent_app_date] => 2008-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4725 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/772/07772907.pdf [firstpage_image] =>[orig_patent_app_number] => 12255170 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8329379 [patent_doc_number] => 08237475 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-08-07 [patent_title] => 'Techniques for generating PVT compensated phase offset to improve accuracy of a locked loop' [patent_app_type] => utility [patent_app_number] => 12/248031 [patent_app_country] => US [patent_app_date] => 2008-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9256 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12248031 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6344140 [patent_doc_number] => 20100085099 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-08 [patent_title] => 'MULTI-PHASE SIGNAL GENERATOR AND METHOD' [patent_app_type] => utility [patent_app_number] => 12/245444 [patent_app_country] => US [patent_app_date] => 2008-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5119 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0085/20100085099.pdf [firstpage_image] =>[orig_patent_app_number] => 12245444 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6344116 [patent_doc_number] => 20100085094 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-08 [patent_title] => 'MULTI-PHASE SIGNAL GENERATOR AND METHOD' [patent_app_type] => utility [patent_app_number] => 12/245407 [patent_app_country] => US [patent_app_date] => 2008-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5489 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0085/20100085094.pdf [firstpage_image] =>[orig_patent_app_number] => 12245407 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4580528 [patent_doc_number] => 07825713 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-02 [patent_title] => 'Absolute time delay generating device' [patent_app_type] => utility [patent_app_number] => 12/286765 [patent_app_country] => US [patent_app_date] => 2008-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3683 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/825/07825713.pdf [firstpage_image] =>[orig_patent_app_number] => 12286765 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8245441 [patent_doc_number] => 08203367 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-06-19 [patent_title] => 'Frequency divider and method for frequency division' [patent_app_type] => utility [patent_app_number] => 12/738405 [patent_app_country] => US [patent_app_date] => 2008-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 5828 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/203/08203367.pdf [firstpage_image] =>[orig_patent_app_number] => 12738405 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5567811 [patent_doc_number] => 20090251189 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-08 [patent_title] => 'Multi-Phase Phase Interpolator' [patent_app_type] => utility [patent_app_number] => 12/207777 [patent_app_country] => US [patent_app_date] => 2008-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5046 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0251/20090251189.pdf [firstpage_image] =>[orig_patent_app_number] => 12207777 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5499852 [patent_doc_number] => 20090160540 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-25 [patent_title] => 'POWER-UP CIRCUIT FOR REDUCING A VARIATION IN TRIGGERING VOLTAGE IN A SEMICONDUCTOR INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/206975 [patent_app_country] => US [patent_app_date] => 2008-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3453 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0160/20090160540.pdf [firstpage_image] =>[orig_patent_app_number] => 12206975 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7505455 [patent_doc_number] => 08035426 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-10-11 [patent_title] => 'Power-on-reset generator using a voltage-shaping inverter chain' [patent_app_type] => utility [patent_app_number] => 12/206485 [patent_app_country] => US [patent_app_date] => 2008-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 5188 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/035/08035426.pdf [firstpage_image] =>[orig_patent_app_number] => 12206485 [rel_patent_id] =>[rel_patent_doc_number] =>)