Search

Branon C. Painter

Examiner (ID: 11060)

Most Active Art Unit
3635
Art Unit(s)
3633, 3635
Total Applications
434
Issued Applications
193
Pending Applications
4
Abandoned Applications
238

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19818920 [patent_doc_number] => 20250077127 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-06 [patent_title] => DATA STORAGE METHOD, STORAGE APPARATUS AND HOST [patent_app_type] => utility [patent_app_number] => 18/952134 [patent_app_country] => US [patent_app_date] => 2024-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11757 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18952134 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/952134
DATA STORAGE METHOD, STORAGE APPARATUS AND HOST Nov 18, 2024 Pending
Array ( [id] => 20123350 [patent_doc_number] => 20250238381 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-24 [patent_title] => DMA DEVICE, OPERATING METHOD THEREOF, AND ELECTRONIC DEVICE INCLUDING DMA DEVICE [patent_app_type] => utility [patent_app_number] => 18/940052 [patent_app_country] => US [patent_app_date] => 2024-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2278 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18940052 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/940052
DMA DEVICE, OPERATING METHOD THEREOF, AND ELECTRONIC DEVICE INCLUDING DMA DEVICE Nov 6, 2024 Pending
Array ( [id] => 19992517 [patent_doc_number] => 20250130739 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-24 [patent_title] => QUAD-DATA-RATE (QDR) HOST INTERFACE IN A MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 18/935798 [patent_app_country] => US [patent_app_date] => 2024-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1279 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18935798 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/935798
QUAD-DATA-RATE (QDR) HOST INTERFACE IN A MEMORY SYSTEM Nov 3, 2024 Pending
Array ( [id] => 20018128 [patent_doc_number] => 20250156350 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-15 [patent_title] => PROTOCOL INCLUDING TIMING CALIBRATION BETWEEN MEMORY REQUEST AND DATA TRANSFER [patent_app_type] => utility [patent_app_number] => 18/920424 [patent_app_country] => US [patent_app_date] => 2024-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1166 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18920424 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/920424
PROTOCOL INCLUDING TIMING CALIBRATION BETWEEN MEMORY REQUEST AND DATA TRANSFER Oct 17, 2024 Pending
Array ( [id] => 19748001 [patent_doc_number] => 20250036566 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-30 [patent_title] => MEMORY PROCESSING UNIT ARCHITECTURE MAPPING TECHNIQUES [patent_app_type] => utility [patent_app_number] => 18/919260 [patent_app_country] => US [patent_app_date] => 2024-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11207 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18919260 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/919260
MEMORY PROCESSING UNIT ARCHITECTURE MAPPING TECHNIQUES Oct 16, 2024 Pending
Array ( [id] => 19748000 [patent_doc_number] => 20250036565 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-30 [patent_title] => MEMORY PROCESSING UNIT CORE ARCHITECTURES [patent_app_type] => utility [patent_app_number] => 18/917509 [patent_app_country] => US [patent_app_date] => 2024-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7377 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -25 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18917509 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/917509
MEMORY PROCESSING UNIT CORE ARCHITECTURES Oct 15, 2024 Pending
Array ( [id] => 20380311 [patent_doc_number] => 20250362804 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-11-27 [patent_title] => DATA INPUT AND OUTPUT METHOD AND SEMICONDUCTOR DEVICE USING THE SAME [patent_app_type] => utility [patent_app_number] => 18/915560 [patent_app_country] => US [patent_app_date] => 2024-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19134 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18915560 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/915560
DATA INPUT AND OUTPUT METHOD AND SEMICONDUCTOR DEVICE USING THE SAME Oct 14, 2024 Pending
Array ( [id] => 20052143 [patent_doc_number] => 20250190365 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-12 [patent_title] => DATA PADDING DEVICE AND DATA PADDING METHOD [patent_app_type] => utility [patent_app_number] => 18/895502 [patent_app_country] => US [patent_app_date] => 2024-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18895502 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/895502
DATA PADDING DEVICE AND DATA PADDING METHOD Sep 24, 2024 Pending
Array ( [id] => 20323005 [patent_doc_number] => 20250335093 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-30 [patent_title] => CONTROLLER AND MEMORY SYSTEM INCLUDING A MAILBOX [patent_app_type] => utility [patent_app_number] => 18/882762 [patent_app_country] => US [patent_app_date] => 2024-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12807 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18882762 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/882762
CONTROLLER AND MEMORY SYSTEM INCLUDING A MAILBOX Sep 11, 2024 Pending
Array ( [id] => 19644846 [patent_doc_number] => 20240419366 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-19 [patent_title] => Constructing Virtual Storage Systems From A Variety Of Components [patent_app_type] => utility [patent_app_number] => 18/821618 [patent_app_country] => US [patent_app_date] => 2024-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 66570 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18821618 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/821618
Constructing Virtual Storage Systems From A Variety Of Components Aug 29, 2024 Pending
Array ( [id] => 19645418 [patent_doc_number] => 20240419938 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-19 [patent_title] => ALLOCATION SYSTEM IN HOSPITAL BY USING GRAPH DATA OF DOCTOR AND PATIENT [patent_app_type] => utility [patent_app_number] => 18/815926 [patent_app_country] => US [patent_app_date] => 2024-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8207 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18815926 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/815926
ALLOCATION SYSTEM IN HOSPITAL BY USING GRAPH DATA OF DOCTOR AND PATIENT Aug 26, 2024 Pending
Array ( [id] => 20388023 [patent_doc_number] => 12487749 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-02 [patent_title] => Flash memory controller, operating method of flash memory controller, and storage device capable of performing different dimension error correction to protect data [patent_app_type] => utility [patent_app_number] => 18/810487 [patent_app_country] => US [patent_app_date] => 2024-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 14755 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18810487 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/810487
Flash memory controller, operating method of flash memory controller, and storage device capable of performing different dimension error correction to protect data Aug 19, 2024 Issued
Array ( [id] => 20094963 [patent_doc_number] => 20250224899 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-10 [patent_title] => STORAGE CONTROLLER AND STORAGE DEVICE INCLUDING THEREOF [patent_app_type] => utility [patent_app_number] => 18/807222 [patent_app_country] => US [patent_app_date] => 2024-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6921 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18807222 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/807222
STORAGE CONTROLLER AND STORAGE DEVICE INCLUDING THEREOF Aug 15, 2024 Pending
Array ( [id] => 19617239 [patent_doc_number] => 20240402919 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-05 [patent_title] => VERIFY FAILBIT COUNT CIRCUIT, MEMORY DEVICE, MEMORY SYSTEM AND METHOD [patent_app_type] => utility [patent_app_number] => 18/802835 [patent_app_country] => US [patent_app_date] => 2024-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16961 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18802835 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/802835
VERIFY FAILBIT COUNT CIRCUIT, MEMORY DEVICE, MEMORY SYSTEM AND METHOD Aug 12, 2024 Pending
Array ( [id] => 20310627 [patent_doc_number] => 20250328256 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-23 [patent_title] => MEMORY SYSTEMS AND METHODS OF OPERATING THEREOF, STORAGE MEDIUMS AND ELECTRONIC APPARATUSES [patent_app_type] => utility [patent_app_number] => 18/784345 [patent_app_country] => US [patent_app_date] => 2024-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4984 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18784345 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/784345
MEMORY SYSTEMS AND METHODS OF OPERATING THEREOF, STORAGE MEDIUMS AND ELECTRONIC APPARATUSES Jul 24, 2024 Pending
Array ( [id] => 19892010 [patent_doc_number] => 20250117322 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-10 [patent_title] => SEGREGATING LOGICAL TO PHYSICAL MAPPINGS [patent_app_type] => utility [patent_app_number] => 18/776215 [patent_app_country] => US [patent_app_date] => 2024-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13394 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18776215 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/776215
SEGREGATING LOGICAL TO PHYSICAL MAPPINGS Jul 16, 2024 Pending
Array ( [id] => 19835508 [patent_doc_number] => 20250087294 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-13 [patent_title] => MEMORY REPAIRS [patent_app_type] => utility [patent_app_number] => 18/775881 [patent_app_country] => US [patent_app_date] => 2024-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5380 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18775881 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/775881
MEMORY REPAIRS Jul 16, 2024 Pending
Array ( [id] => 20182149 [patent_doc_number] => 20250266107 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-21 [patent_title] => STORAGE APPARATUS INCLUDING WORD LINE GROUPING DEVICE AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/774938 [patent_app_country] => US [patent_app_date] => 2024-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5077 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18774938 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/774938
STORAGE APPARATUS INCLUDING WORD LINE GROUPING DEVICE AND OPERATING METHOD THEREOF Jul 16, 2024 Pending
Array ( [id] => 20234196 [patent_doc_number] => 20250291515 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-18 [patent_title] => STORAGE DEVICE AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/774792 [patent_app_country] => US [patent_app_date] => 2024-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3680 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18774792 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/774792
STORAGE DEVICE AND OPERATING METHOD THEREOF Jul 15, 2024 Pending
Array ( [id] => 20043017 [patent_doc_number] => 20250181239 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-05 [patent_title] => STACK MEMORY DEVICES CONFIGURED TO COMMUNICATE VIA PACKETS [patent_app_type] => utility [patent_app_number] => 18/771088 [patent_app_country] => US [patent_app_date] => 2024-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19619 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18771088 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/771088
STACK MEMORY DEVICES CONFIGURED TO COMMUNICATE VIA PACKETS Jul 11, 2024 Pending
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