Search

Branon C. Painter

Examiner (ID: 11060)

Most Active Art Unit
3635
Art Unit(s)
3633, 3635
Total Applications
434
Issued Applications
193
Pending Applications
4
Abandoned Applications
238

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18257112 [patent_doc_number] => 20230084152 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-16 [patent_title] => SCHEDULING MEDIA MANAGEMENT OPERATIONS BASED ON DETERMINED HOST SYSTEM USAGE REQUIREMENTS [patent_app_type] => utility [patent_app_number] => 18/051462 [patent_app_country] => US [patent_app_date] => 2022-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8386 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18051462 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/051462
Scheduling media management operations based on determined host system usage requirements Oct 30, 2022 Issued
Array ( [id] => 19028698 [patent_doc_number] => 11928055 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-12 [patent_title] => Memory sub-system for decoding non-power-of-two addressable unit address boundaries [patent_app_type] => utility [patent_app_number] => 17/975164 [patent_app_country] => US [patent_app_date] => 2022-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5659 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17975164 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/975164
Memory sub-system for decoding non-power-of-two addressable unit address boundaries Oct 26, 2022 Issued
Array ( [id] => 19228616 [patent_doc_number] => 12008253 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-11 [patent_title] => Embedded system and method for updating firmware [patent_app_type] => utility [patent_app_number] => 17/966002 [patent_app_country] => US [patent_app_date] => 2022-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 6454 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17966002 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/966002
Embedded system and method for updating firmware Oct 13, 2022 Issued
Array ( [id] => 19182870 [patent_doc_number] => 11989460 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-21 [patent_title] => Capacity expansion in a virtual storage appliance [patent_app_type] => utility [patent_app_number] => 17/965262 [patent_app_country] => US [patent_app_date] => 2022-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7590 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17965262 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/965262
Capacity expansion in a virtual storage appliance Oct 12, 2022 Issued
Array ( [id] => 18229148 [patent_doc_number] => 20230068142 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => EXTENDED UTILIZATION AREA FOR A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/045067 [patent_app_country] => US [patent_app_date] => 2022-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4494 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18045067 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/045067
Extended utilization area for a memory device Oct 6, 2022 Issued
Array ( [id] => 19625975 [patent_doc_number] => 12164808 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-10 [patent_title] => Quad-data-rate (QDR) host interface in a memory system [patent_app_type] => utility [patent_app_number] => 17/962362 [patent_app_country] => US [patent_app_date] => 2022-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 6501 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17962362 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/962362
Quad-data-rate (QDR) host interface in a memory system Oct 6, 2022 Issued
Array ( [id] => 18577340 [patent_doc_number] => 11733869 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-22 [patent_title] => Apparatus and method to share host system RAM with mass storage memory RAM [patent_app_type] => utility [patent_app_number] => 17/937901 [patent_app_country] => US [patent_app_date] => 2022-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4891 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17937901 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/937901
Apparatus and method to share host system RAM with mass storage memory RAM Oct 3, 2022 Issued
Array ( [id] => 18296270 [patent_doc_number] => 20230105956 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-06 [patent_title] => APPARATUSES AND METHODS FOR CONCURRENTLY ACCESSING DIFFERENT MEMORY PLANES OF A MEMORY [patent_app_type] => utility [patent_app_number] => 17/959078 [patent_app_country] => US [patent_app_date] => 2022-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5754 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17959078 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/959078
Apparatuses and methods for concurrently accessing different memory planes of a memory Oct 2, 2022 Issued
Array ( [id] => 18164366 [patent_doc_number] => 20230030961 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-02 [patent_title] => VIRTUALIZATION-BASED PLATFORM PROTECTION TECHNOLOGY [patent_app_type] => utility [patent_app_number] => 17/937010 [patent_app_country] => US [patent_app_date] => 2022-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17931 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17937010 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/937010
VIRTUALIZATION-BASED PLATFORM PROTECTION TECHNOLOGY Sep 29, 2022 Abandoned
Array ( [id] => 18677662 [patent_doc_number] => 20230315308 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-05 [patent_title] => STORAGE DEVICE AND METHOD OF OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 17/953829 [patent_app_country] => US [patent_app_date] => 2022-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11858 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17953829 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/953829
STORAGE DEVICE AND METHOD OF OPERATING THE SAME Sep 26, 2022 Pending
Array ( [id] => 18240701 [patent_doc_number] => 20230073012 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-09 [patent_title] => MEMORY PROCESSING UNIT CORE ARCHITECTURES [patent_app_type] => utility [patent_app_number] => 17/943116 [patent_app_country] => US [patent_app_date] => 2022-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7111 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17943116 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/943116
Memory processing unit core architectures Sep 11, 2022 Issued
Array ( [id] => 19293479 [patent_doc_number] => 12032833 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-09 [patent_title] => Management of error-handling flows in memory devices using probability data structure [patent_app_type] => utility [patent_app_number] => 17/943082 [patent_app_country] => US [patent_app_date] => 2022-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7961 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17943082 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/943082
Management of error-handling flows in memory devices using probability data structure Sep 11, 2022 Issued
Array ( [id] => 18734591 [patent_doc_number] => 11803321 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-31 [patent_title] => Interruption of program operations at a memory sub-system [patent_app_type] => utility [patent_app_number] => 17/943113 [patent_app_country] => US [patent_app_date] => 2022-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7688 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17943113 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/943113
Interruption of program operations at a memory sub-system Sep 11, 2022 Issued
Array ( [id] => 19810988 [patent_doc_number] => 12242380 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-04 [patent_title] => Memory processing unit architectures and configurations [patent_app_type] => utility [patent_app_number] => 17/943100 [patent_app_country] => US [patent_app_date] => 2022-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 47 [patent_no_of_words] => 9088 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17943100 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/943100
Memory processing unit architectures and configurations Sep 11, 2022 Issued
Array ( [id] => 20131030 [patent_doc_number] => 12373343 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-29 [patent_title] => Inter-layer communication techniques for memory processing unit architectures [patent_app_type] => utility [patent_app_number] => 17/943143 [patent_app_country] => US [patent_app_date] => 2022-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 51 [patent_no_of_words] => 5910 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17943143 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/943143
Inter-layer communication techniques for memory processing unit architectures Sep 11, 2022 Issued
Array ( [id] => 19523007 [patent_doc_number] => 12124734 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-22 [patent_title] => Method and system to process data delete in virtualized computing [patent_app_type] => utility [patent_app_number] => 17/943142 [patent_app_country] => US [patent_app_date] => 2022-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5633 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17943142 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/943142
Method and system to process data delete in virtualized computing Sep 11, 2022 Issued
Array ( [id] => 19718910 [patent_doc_number] => 12204447 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-21 [patent_title] => Memory processing unit architecture mapping techniques [patent_app_type] => utility [patent_app_number] => 17/943119 [patent_app_country] => US [patent_app_date] => 2022-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 46 [patent_no_of_words] => 10986 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17943119 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/943119
Memory processing unit architecture mapping techniques Sep 11, 2022 Issued
Array ( [id] => 19005653 [patent_doc_number] => 20240069724 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-29 [patent_title] => STORAGE DEVICE PROJECTED TEMPERATURE ENVIRONMENT CONFIGURATION SYSTEM [patent_app_type] => utility [patent_app_number] => 17/900209 [patent_app_country] => US [patent_app_date] => 2022-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8951 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17900209 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/900209
Storage device projected temperature environment configuration system Aug 30, 2022 Issued
Array ( [id] => 19005732 [patent_doc_number] => 20240069803 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-29 [patent_title] => IN-PLACE WRITE TECHNIQUES WITHOUT ERASE IN A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/898639 [patent_app_country] => US [patent_app_date] => 2022-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13054 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17898639 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/898639
In-place write techniques without erase in a memory device Aug 29, 2022 Issued
Array ( [id] => 19078458 [patent_doc_number] => 11947826 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-02 [patent_title] => Method for accelerating image storing and retrieving differential latency storage devices based on access rates [patent_app_type] => utility [patent_app_number] => 17/891128 [patent_app_country] => US [patent_app_date] => 2022-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 33 [patent_no_of_words] => 31044 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17891128 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/891128
Method for accelerating image storing and retrieving differential latency storage devices based on access rates Aug 17, 2022 Issued
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