
Brett A. Feeney
Supervisory Patent Examiner (ID: 17467, Phone: (571)270-5484 , Office: P/2822 )
| Most Active Art Unit | 3683 |
| Art Unit(s) | 2822, 2898, 3683, 3624 |
| Total Applications | 276 |
| Issued Applications | 122 |
| Pending Applications | 0 |
| Abandoned Applications | 154 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 10472215
[patent_doc_number] => 20150357231
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-12-10
[patent_title] => 'Method of Manufacturing Semiconductor Device'
[patent_app_type] => utility
[patent_app_number] => 14/830573
[patent_app_country] => US
[patent_app_date] => 2015-08-19
[patent_effective_date] => 0000-00-00
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[patent_figures_cnt] => 23
[patent_no_of_words] => 14837
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[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14830573
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/830573 | Method of Manufacturing Semiconductor Device | Aug 18, 2015 | Abandoned |
Array
(
[id] => 11599655
[patent_doc_number] => 09646832
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-05-09
[patent_title] => 'Porous fin as compliant medium to form dislocation-free heteroepitaxial films'
[patent_app_type] => utility
[patent_app_number] => 14/812797
[patent_app_country] => US
[patent_app_date] => 2015-07-29
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/812797 | Porous fin as compliant medium to form dislocation-free heteroepitaxial films | Jul 28, 2015 | Issued |
Array
(
[id] => 10448173
[patent_doc_number] => 20150333187
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-11-19
[patent_title] => 'THIN FILM HYBRID JUNCTION FIELD EFFECT TRANSISTOR'
[patent_app_type] => utility
[patent_app_number] => 14/809984
[patent_app_country] => US
[patent_app_date] => 2015-07-27
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/809984 | THIN FILM HYBRID JUNCTION FIELD EFFECT TRANSISTOR | Jul 26, 2015 | Abandoned |
Array
(
[id] => 10426152
[patent_doc_number] => 20150311163
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-10-29
[patent_title] => 'Anchoring Structure and Intermeshing Structure'
[patent_app_type] => utility
[patent_app_number] => 14/791026
[patent_app_country] => US
[patent_app_date] => 2015-07-02
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/791026 | Anchoring Structure and Intermeshing Structure | Jul 1, 2015 | Abandoned |
Array
(
[id] => 13755525
[patent_doc_number] => 10170718
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[patent_kind] => B2
[patent_issue_date] => 2019-01-01
[patent_title] => Electronic devices employing aligned organic polymers
[patent_app_type] => utility
[patent_app_number] => 14/725810
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/725810 | Electronic devices employing aligned organic polymers | May 28, 2015 | Issued |
Array
(
[id] => 11087878
[patent_doc_number] => 20160284846
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[patent_kind] => A1
[patent_issue_date] => 2016-09-29
[patent_title] => 'FORMING TUNNELING FIELD-EFFECT TRANSISTOR WITH STACKING FAULT AND RESULTING DEVICE'
[patent_app_type] => utility
[patent_app_number] => 14/667872
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/667872 | FORMING TUNNELING FIELD-EFFECT TRANSISTOR WITH STACKING FAULT AND RESULTING DEVICE | Mar 24, 2015 | Abandoned |
Array
(
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[patent_title] => 'SEMICONDUCTOR DEVICE COMPRISING BURIED GATE AND METHOD FOR FABRICATING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 14/532762
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/532762 | SEMICONDUCTOR DEVICE COMPRISING BURIED GATE AND METHOD FOR FABRICATING THE SAME | Nov 3, 2014 | Abandoned |
Array
(
[id] => 9901607
[patent_doc_number] => 20150056807
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-02-26
[patent_title] => 'SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF'
[patent_app_type] => utility
[patent_app_number] => 14/531738
[patent_app_country] => US
[patent_app_date] => 2014-11-03
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/531738 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF | Nov 2, 2014 | Abandoned |
Array
(
[id] => 10772235
[patent_doc_number] => 20160118391
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-04-28
[patent_title] => 'DEUTERIUM ANNEAL OF SEMICONDUCTOR CHANNELS IN A THREE-DIMENSIONAL MEMORY STRUCTURE'
[patent_app_type] => utility
[patent_app_number] => 14/521136
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/521136 | DEUTERIUM ANNEAL OF SEMICONDUCTOR CHANNELS IN A THREE-DIMENSIONAL MEMORY STRUCTURE | Oct 21, 2014 | Abandoned |
Array
(
[id] => 10964712
[patent_doc_number] => 20140367744
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-12-18
[patent_title] => 'Monolithic Integrated Composite Group III-V and Group IV Semiconductor Device and IC'
[patent_app_type] => utility
[patent_app_number] => 14/472974
[patent_app_country] => US
[patent_app_date] => 2014-08-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/472974 | Monolithic Integrated Composite Group III-V and Group IV Semiconductor Device and IC | Aug 28, 2014 | Abandoned |
Array
(
[id] => 11010806
[patent_doc_number] => 20160207759
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-07-21
[patent_title] => 'MOLDED LEAD FRAME PACKAGE WITH EMBEDDED DIE'
[patent_app_type] => utility
[patent_app_number] => 14/915032
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/915032 | Molded lead frame package with embedded die | Aug 28, 2014 | Issued |
Array
(
[id] => 10957964
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/466755 | LASER DICING METHOD | Aug 21, 2014 | Abandoned |
Array
(
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Array
(
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Array
(
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Array
(
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Array
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Array
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Array
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Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/203531 | Geo-spatially constrained private neighborhood social network | Mar 9, 2014 | Issued |