
Brian D. Nguyen
Examiner (ID: 13851, Phone: (571)272-3084 , Office: P/2472 )
| Most Active Art Unit | 2472 |
| Art Unit(s) | 2472, 2416, 2475, 2732, 2616, 2661 |
| Total Applications | 2155 |
| Issued Applications | 1859 |
| Pending Applications | 154 |
| Abandoned Applications | 165 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4094161
[patent_doc_number] => 06096577
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-08-01
[patent_title] => 'Method of making semiconductor device, and film carrier tape'
[patent_app_type] => 1
[patent_app_number] => 9/180896
[patent_app_country] => US
[patent_app_date] => 1999-01-15
[patent_effective_date] => 0000-00-00
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[patent_no_of_words] => 4001
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[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/096/06096577.pdf
[firstpage_image] =>[orig_patent_app_number] => 180896
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/180896 | Method of making semiconductor device, and film carrier tape | Jan 14, 1999 | Issued |
Array
(
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[patent_doc_number] => 06228762
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-05-08
[patent_title] => 'Methods for forming contact holes having sidewalls with smooth profiles'
[patent_app_type] => 1
[patent_app_number] => 9/231339
[patent_app_country] => US
[patent_app_date] => 1999-01-13
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/231339 | Methods for forming contact holes having sidewalls with smooth profiles | Jan 12, 1999 | Issued |
Array
(
[id] => 4235202
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[patent_kind] => NA
[patent_issue_date] => 2000-11-07
[patent_title] => 'Multi-chip semiconductor device and method of producing the same'
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[patent_app_date] => 1999-01-11
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Array
(
[id] => 4099600
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[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-05-23
[patent_title] => 'Semiconductor device, method of fabricating the same, and electronic apparatus'
[patent_app_type] => 1
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Array
(
[id] => 4100075
[patent_doc_number] => 06066546
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-05-23
[patent_title] => 'Method to minimize particulate induced clamping failures'
[patent_app_type] => 1
[patent_app_number] => 9/227644
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[firstpage_image] =>[orig_patent_app_number] => 227644
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/227644 | Method to minimize particulate induced clamping failures | Jan 7, 1999 | Issued |
Array
(
[id] => 4357874
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[patent_kind] => NA
[patent_issue_date] => 2001-07-03
[patent_title] => 'Process for manufacturing patterned silicon-on-insulator layers with self-aligned trenches and resulting product'
[patent_app_type] => 1
[patent_app_number] => 9/227696
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[firstpage_image] =>[orig_patent_app_number] => 227696
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/227696 | Process for manufacturing patterned silicon-on-insulator layers with self-aligned trenches and resulting product | Jan 7, 1999 | Issued |
Array
(
[id] => 4404338
[patent_doc_number] => 06271058
[patent_country] => US
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[patent_title] => 'Method of manufacturing semiconductor device in which semiconductor chip is mounted facedown on board'
[patent_app_type] => 1
[patent_app_number] => 9/225446
[patent_app_country] => US
[patent_app_date] => 1999-01-06
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Array
(
[id] => 4214153
[patent_doc_number] => 06110762
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-08-29
[patent_title] => 'Method of manufacturing a custom corner attach heat sink design for a plastic ball grid array integrated circuit package'
[patent_app_type] => 1
[patent_app_number] => 9/225416
[patent_app_country] => US
[patent_app_date] => 1999-01-05
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 225416
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/225416 | Method of manufacturing a custom corner attach heat sink design for a plastic ball grid array integrated circuit package | Jan 4, 1999 | Issued |
Array
(
[id] => 4348915
[patent_doc_number] => 06214750
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-04-10
[patent_title] => 'Alternative structure to SOI using proton beams'
[patent_app_type] => 1
[patent_app_number] => 9/225376
[patent_app_country] => US
[patent_app_date] => 1999-01-04
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/225376 | Alternative structure to SOI using proton beams | Jan 3, 1999 | Issued |
Array
(
[id] => 4327326
[patent_doc_number] => 06319818
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-11-20
[patent_title] => 'Pattern factor checkerboard for planarization'
[patent_app_type] => 1
[patent_app_number] => 9/224778
[patent_app_country] => US
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[firstpage_image] =>[orig_patent_app_number] => 224778
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/224778 | Pattern factor checkerboard for planarization | Jan 3, 1999 | Issued |
Array
(
[id] => 4369326
[patent_doc_number] => 06287961
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-09-11
[patent_title] => 'Dual damascene patterned conductor layer formation method without etch stop layer'
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[patent_app_number] => 9/225380
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/225380 | Dual damascene patterned conductor layer formation method without etch stop layer | Jan 3, 1999 | Issued |
Array
(
[id] => 4287102
[patent_doc_number] => 06211097
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[patent_kind] => NA
[patent_issue_date] => 2001-04-03
[patent_title] => 'Planarization process'
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[patent_app_date] => 1998-12-30
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[firstpage_image] =>[orig_patent_app_number] => 223398
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Array
(
[id] => 3942040
[patent_doc_number] => 05989994
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[patent_issue_date] => 1999-11-23
[patent_title] => 'Method for producing contact structures'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/222176 | Method for producing contact structures | Dec 28, 1998 | Issued |
Array
(
[id] => 4107111
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Array
(
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[patent_title] => 'Method for packaging integrated circuits with elastomer chip carriers'
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Array
(
[id] => 4287073
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[firstpage_image] =>[orig_patent_app_number] => 221025
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Array
(
[id] => 4350152
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[patent_issue_date] => 2001-09-18
[patent_title] => 'Method for protecting gate oxide layer and monitoring damage'
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Array
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Array
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Array
(
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[firstpage_image] =>[orig_patent_app_number] => 208025
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/208025 | Method of forming bonding pad | Dec 8, 1998 | Issued |