Search

Brian D. Nguyen

Examiner (ID: 13851, Phone: (571)272-3084 , Office: P/2472 )

Most Active Art Unit
2472
Art Unit(s)
2472, 2416, 2475, 2732, 2616, 2661
Total Applications
2155
Issued Applications
1859
Pending Applications
154
Abandoned Applications
165

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3934683 [patent_doc_number] => 05972736 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-26 [patent_title] => 'Integrated circuit package and method' [patent_app_type] => 1 [patent_app_number] => 9/205424 [patent_app_country] => US [patent_app_date] => 1998-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 2470 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/972/05972736.pdf [firstpage_image] =>[orig_patent_app_number] => 205424 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/205424
Integrated circuit package and method Dec 3, 1998 Issued
Array ( [id] => 4154924 [patent_doc_number] => 06114191 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-05 [patent_title] => 'Semiconductor packaging method' [patent_app_type] => 1 [patent_app_number] => 9/204904 [patent_app_country] => US [patent_app_date] => 1998-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 15 [patent_no_of_words] => 2698 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/114/06114191.pdf [firstpage_image] =>[orig_patent_app_number] => 204904 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/204904
Semiconductor packaging method Dec 2, 1998 Issued
Array ( [id] => 4155495 [patent_doc_number] => 06114229 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-05 [patent_title] => 'Polysilicon gate electrode critical dimension and drive current control in MOS transistor fabrication' [patent_app_type] => 1 [patent_app_number] => 9/196845 [patent_app_country] => US [patent_app_date] => 1998-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2084 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/114/06114229.pdf [firstpage_image] =>[orig_patent_app_number] => 196845 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/196845
Polysilicon gate electrode critical dimension and drive current control in MOS transistor fabrication Nov 19, 1998 Issued
Array ( [id] => 1474624 [patent_doc_number] => 06387794 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-05-14 [patent_title] => 'Electrode structure for semiconductor device, method for forming the same, mounted body including semiconductor device and semiconductor device' [patent_app_type] => B2 [patent_app_number] => 09/197334 [patent_app_country] => US [patent_app_date] => 1998-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 5018 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/387/06387794.pdf [firstpage_image] =>[orig_patent_app_number] => 09197334 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/197334
Electrode structure for semiconductor device, method for forming the same, mounted body including semiconductor device and semiconductor device Nov 18, 1998 Issued
Array ( [id] => 4102565 [patent_doc_number] => 06051481 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-18 [patent_title] => 'Method and device for bonding two plate-shaped objects' [patent_app_type] => 1 [patent_app_number] => 9/196066 [patent_app_country] => US [patent_app_date] => 1998-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 6201 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/051/06051481.pdf [firstpage_image] =>[orig_patent_app_number] => 196066 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/196066
Method and device for bonding two plate-shaped objects Nov 18, 1998 Issued
Array ( [id] => 4097635 [patent_doc_number] => 06048755 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-11 [patent_title] => 'Method for fabricating BGA package using substrate with patterned solder mask open in die attach area' [patent_app_type] => 1 [patent_app_number] => 9/191215 [patent_app_country] => US [patent_app_date] => 1998-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 21 [patent_no_of_words] => 4297 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/048/06048755.pdf [firstpage_image] =>[orig_patent_app_number] => 191215 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/191215
Method for fabricating BGA package using substrate with patterned solder mask open in die attach area Nov 11, 1998 Issued
Array ( [id] => 4289172 [patent_doc_number] => 06235553 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-22 [patent_title] => 'Method and system for creating and using an electrostatic discharge (ESD) protected logotype contact module with a smart card' [patent_app_type] => 1 [patent_app_number] => 9/190265 [patent_app_country] => US [patent_app_date] => 1998-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5014 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/235/06235553.pdf [firstpage_image] =>[orig_patent_app_number] => 190265 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/190265
Method and system for creating and using an electrostatic discharge (ESD) protected logotype contact module with a smart card Nov 11, 1998 Issued
Array ( [id] => 4172108 [patent_doc_number] => 06083770 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-04 [patent_title] => 'Thermoelectric piece and process of making the same' [patent_app_type] => 1 [patent_app_number] => 9/068456 [patent_app_country] => US [patent_app_date] => 1998-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 15 [patent_no_of_words] => 5174 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/083/06083770.pdf [firstpage_image] =>[orig_patent_app_number] => 068456 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/068456
Thermoelectric piece and process of making the same Nov 9, 1998 Issued
Array ( [id] => 4353150 [patent_doc_number] => 06218205 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-17 [patent_title] => 'Post-process depositing shielding for microelectromechanical systems' [patent_app_type] => 1 [patent_app_number] => 9/169494 [patent_app_country] => US [patent_app_date] => 1998-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2437 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/218/06218205.pdf [firstpage_image] =>[orig_patent_app_number] => 169494 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/169494
Post-process depositing shielding for microelectromechanical systems Oct 8, 1998 Issued
Array ( [id] => 4407713 [patent_doc_number] => 06300148 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-09 [patent_title] => 'Semiconductor structure with a backside protective layer and backside probes and a method for constructing the structure' [patent_app_type] => 1 [patent_app_number] => 9/166266 [patent_app_country] => US [patent_app_date] => 1998-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3366 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/300/06300148.pdf [firstpage_image] =>[orig_patent_app_number] => 166266 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/166266
Semiconductor structure with a backside protective layer and backside probes and a method for constructing the structure Oct 4, 1998 Issued
Array ( [id] => 4063650 [patent_doc_number] => 06008074 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-28 [patent_title] => 'Method of forming a synchronous-link dynamic random access memory edge-mounted device' [patent_app_type] => 1 [patent_app_number] => 9/164605 [patent_app_country] => US [patent_app_date] => 1998-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 3325 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/008/06008074.pdf [firstpage_image] =>[orig_patent_app_number] => 164605 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/164605
Method of forming a synchronous-link dynamic random access memory edge-mounted device Sep 30, 1998 Issued
Array ( [id] => 4081057 [patent_doc_number] => 06054371 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-25 [patent_title] => 'Method of manufacturing a semiconductor device by detachably mounting substrates to a holder board' [patent_app_type] => 1 [patent_app_number] => 9/162155 [patent_app_country] => US [patent_app_date] => 1998-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 16 [patent_no_of_words] => 9524 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/054/06054371.pdf [firstpage_image] =>[orig_patent_app_number] => 162155 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/162155
Method of manufacturing a semiconductor device by detachably mounting substrates to a holder board Sep 28, 1998 Issued
Array ( [id] => 4003910 [patent_doc_number] => 05960262 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-28 [patent_title] => 'Stitch bond enhancement for hard-to-bond materials' [patent_app_type] => 1 [patent_app_number] => 9/158845 [patent_app_country] => US [patent_app_date] => 1998-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 6 [patent_no_of_words] => 1216 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/960/05960262.pdf [firstpage_image] =>[orig_patent_app_number] => 158845 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/158845
Stitch bond enhancement for hard-to-bond materials Sep 22, 1998 Issued
Array ( [id] => 4083379 [patent_doc_number] => 06162653 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-19 [patent_title] => 'Lead frame attachment for optoelectronic device' [patent_app_type] => 1 [patent_app_number] => 9/159256 [patent_app_country] => US [patent_app_date] => 1998-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 13 [patent_no_of_words] => 2734 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/162/06162653.pdf [firstpage_image] =>[orig_patent_app_number] => 159256 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/159256
Lead frame attachment for optoelectronic device Sep 22, 1998 Issued
Array ( [id] => 4408328 [patent_doc_number] => 06228683 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-08 [patent_title] => 'High density leaded ball-grid array package' [patent_app_type] => 1 [patent_app_number] => 9/158685 [patent_app_country] => US [patent_app_date] => 1998-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 8 [patent_no_of_words] => 2135 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/228/06228683.pdf [firstpage_image] =>[orig_patent_app_number] => 158685 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/158685
High density leaded ball-grid array package Sep 21, 1998 Issued
Array ( [id] => 4304254 [patent_doc_number] => 06326300 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-04 [patent_title] => 'Dual damascene patterned conductor layer formation method' [patent_app_type] => 1 [patent_app_number] => 9/157437 [patent_app_country] => US [patent_app_date] => 1998-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 7314 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 337 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/326/06326300.pdf [firstpage_image] =>[orig_patent_app_number] => 157437 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/157437
Dual damascene patterned conductor layer formation method Sep 20, 1998 Issued
Array ( [id] => 4407587 [patent_doc_number] => 06239017 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-29 [patent_title] => 'Dual damascene CMP process with BPSG reflowed contact hole' [patent_app_type] => 1 [patent_app_number] => 9/156357 [patent_app_country] => US [patent_app_date] => 1998-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 3965 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/239/06239017.pdf [firstpage_image] =>[orig_patent_app_number] => 156357 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/156357
Dual damascene CMP process with BPSG reflowed contact hole Sep 17, 1998 Issued
Array ( [id] => 4357492 [patent_doc_number] => 06174803 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-16 [patent_title] => 'Integrated circuit device interconnection techniques' [patent_app_type] => 1 [patent_app_number] => 9/154050 [patent_app_country] => US [patent_app_date] => 1998-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 27 [patent_no_of_words] => 8473 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/174/06174803.pdf [firstpage_image] =>[orig_patent_app_number] => 154050 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/154050
Integrated circuit device interconnection techniques Sep 15, 1998 Issued
Array ( [id] => 3956913 [patent_doc_number] => 05930602 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-27 [patent_title] => 'Leadframe finger support' [patent_app_type] => 1 [patent_app_number] => 9/153366 [patent_app_country] => US [patent_app_date] => 1998-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 858 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/930/05930602.pdf [firstpage_image] =>[orig_patent_app_number] => 153366 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/153366
Leadframe finger support Sep 14, 1998 Issued
Array ( [id] => 4116370 [patent_doc_number] => 06071756 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-06 [patent_title] => 'Method for holding components in place during soldering' [patent_app_type] => 1 [patent_app_number] => 9/137466 [patent_app_country] => US [patent_app_date] => 1998-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 4680 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/071/06071756.pdf [firstpage_image] =>[orig_patent_app_number] => 137466 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/137466
Method for holding components in place during soldering Aug 19, 1998 Issued
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