Search

Brian D. Nguyen

Examiner (ID: 13851, Phone: (571)272-3084 , Office: P/2472 )

Most Active Art Unit
2472
Art Unit(s)
2472, 2416, 2475, 2732, 2616, 2661
Total Applications
2155
Issued Applications
1859
Pending Applications
154
Abandoned Applications
165

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1565975 [patent_doc_number] => 06376355 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-23 [patent_title] => 'Method for forming metal interconnection in semiconductor device' [patent_app_type] => B1 [patent_app_number] => 09/136798 [patent_app_country] => US [patent_app_date] => 1998-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 5951 [patent_no_of_claims] => 66 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/376/06376355.pdf [firstpage_image] =>[orig_patent_app_number] => 09136798 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/136798
Method for forming metal interconnection in semiconductor device Aug 18, 1998 Issued
Array ( [id] => 4303132 [patent_doc_number] => 06187676 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-13 [patent_title] => 'Integrated circuit insulated electrode forming methods using metal silicon nitride layers, and insulated electrodes so formed' [patent_app_type] => 1 [patent_app_number] => 9/134848 [patent_app_country] => US [patent_app_date] => 1998-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 3624 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/187/06187676.pdf [firstpage_image] =>[orig_patent_app_number] => 134848 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/134848
Integrated circuit insulated electrode forming methods using metal silicon nitride layers, and insulated electrodes so formed Aug 13, 1998 Issued
Array ( [id] => 4181732 [patent_doc_number] => 06150187 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-21 [patent_title] => 'Encapsulation method of a polymer or organic light emitting device' [patent_app_type] => 1 [patent_app_number] => 9/122755 [patent_app_country] => US [patent_app_date] => 1998-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1734 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/150/06150187.pdf [firstpage_image] =>[orig_patent_app_number] => 122755 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/122755
Encapsulation method of a polymer or organic light emitting device Jul 26, 1998 Issued
09/114725 DIE ATTACHMENT WITH REDUCED ADHESIVE BLEED-OUT Jul 12, 1998 Abandoned
Array ( [id] => 4368364 [patent_doc_number] => 06287893 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-11 [patent_title] => 'Method for forming chip scale package' [patent_app_type] => 1 [patent_app_number] => 9/114204 [patent_app_country] => US [patent_app_date] => 1998-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 5628 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 312 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/287/06287893.pdf [firstpage_image] =>[orig_patent_app_number] => 114204 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/114204
Method for forming chip scale package Jul 12, 1998 Issued
Array ( [id] => 4125408 [patent_doc_number] => 06127263 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-03 [patent_title] => 'Misalignment tolerant techniques for dual damascene fabrication' [patent_app_type] => 1 [patent_app_number] => 9/113578 [patent_app_country] => US [patent_app_date] => 1998-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 31 [patent_no_of_words] => 7416 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/127/06127263.pdf [firstpage_image] =>[orig_patent_app_number] => 113578 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/113578
Misalignment tolerant techniques for dual damascene fabrication Jul 9, 1998 Issued
Array ( [id] => 4294465 [patent_doc_number] => 06184121 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-06 [patent_title] => 'Chip interconnect wiring structure with low dielectric constant insulator and methods for fabricating the same' [patent_app_type] => 1 [patent_app_number] => 9/112919 [patent_app_country] => US [patent_app_date] => 1998-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 6866 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/184/06184121.pdf [firstpage_image] =>[orig_patent_app_number] => 112919 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/112919
Chip interconnect wiring structure with low dielectric constant insulator and methods for fabricating the same Jul 8, 1998 Issued
Array ( [id] => 1565026 [patent_doc_number] => 06339026 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-15 [patent_title] => 'Semiconductor processing methods of polishing aluminum-comprising layers' [patent_app_type] => B1 [patent_app_number] => 09/066614 [patent_app_country] => US [patent_app_date] => 1998-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 1864 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 35 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/339/06339026.pdf [firstpage_image] =>[orig_patent_app_number] => 09066614 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/066614
Semiconductor processing methods of polishing aluminum-comprising layers Apr 23, 1998 Issued
Array ( [id] => 4197810 [patent_doc_number] => 06013572 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-11 [patent_title] => 'Methods of fabricating and testing silver-tin alloy solder bumps' [patent_app_type] => 1 [patent_app_number] => 9/063716 [patent_app_country] => US [patent_app_date] => 1998-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 4322 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/013/06013572.pdf [firstpage_image] =>[orig_patent_app_number] => 063716 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/063716
Methods of fabricating and testing silver-tin alloy solder bumps Apr 20, 1998 Issued
Array ( [id] => 4191721 [patent_doc_number] => 06130160 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-10 [patent_title] => 'Methods, complexes and system for forming metal-containing films' [patent_app_type] => 1 [patent_app_number] => 9/063193 [patent_app_country] => US [patent_app_date] => 1998-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 6354 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/130/06130160.pdf [firstpage_image] =>[orig_patent_app_number] => 063193 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/063193
Methods, complexes and system for forming metal-containing films Apr 19, 1998 Issued
Array ( [id] => 4222354 [patent_doc_number] => 06010951 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-04 [patent_title] => 'Dual side fabricated semiconductor wafer' [patent_app_type] => 1 [patent_app_number] => 9/060004 [patent_app_country] => US [patent_app_date] => 1998-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 2898 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/010/06010951.pdf [firstpage_image] =>[orig_patent_app_number] => 060004 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/060004
Dual side fabricated semiconductor wafer Apr 13, 1998 Issued
09/033938 ASSEMBLY AND METHOD OF INTERCONNECTING USING BUMPS WITH RIGID INNER CORE Mar 1, 1998 Abandoned
Array ( [id] => 4233427 [patent_doc_number] => 06117771 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-12 [patent_title] => 'Method for depositing cobalt' [patent_app_type] => 1 [patent_app_number] => 9/032194 [patent_app_country] => US [patent_app_date] => 1998-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2585 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/117/06117771.pdf [firstpage_image] =>[orig_patent_app_number] => 032194 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/032194
Method for depositing cobalt Feb 26, 1998 Issued
Array ( [id] => 4222516 [patent_doc_number] => 06010961 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-04 [patent_title] => 'Methods of establishing electrical communication with substrate node locations, semiconductor processing methods of forming dynamic random access memory (DRAM) circuitry, and semiconductor assemblies' [patent_app_type] => 1 [patent_app_number] => 9/031095 [patent_app_country] => US [patent_app_date] => 1998-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 1678 [patent_no_of_claims] => 55 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/010/06010961.pdf [firstpage_image] =>[orig_patent_app_number] => 031095 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/031095
Methods of establishing electrical communication with substrate node locations, semiconductor processing methods of forming dynamic random access memory (DRAM) circuitry, and semiconductor assemblies Feb 25, 1998 Issued
Array ( [id] => 4237935 [patent_doc_number] => 06080616 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-27 [patent_title] => 'Methods of fabricating memory cells with reduced area capacitor interconnect' [patent_app_type] => 1 [patent_app_number] => 9/025905 [patent_app_country] => US [patent_app_date] => 1998-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 4016 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/080/06080616.pdf [firstpage_image] =>[orig_patent_app_number] => 025905 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/025905
Methods of fabricating memory cells with reduced area capacitor interconnect Feb 18, 1998 Issued
Array ( [id] => 4422783 [patent_doc_number] => 06194785 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-27 [patent_title] => 'Method for circuitizing through-holes by photo-activated seeding' [patent_app_type] => 1 [patent_app_number] => 9/023554 [patent_app_country] => US [patent_app_date] => 1998-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 6153 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/194/06194785.pdf [firstpage_image] =>[orig_patent_app_number] => 023554 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/023554
Method for circuitizing through-holes by photo-activated seeding Feb 12, 1998 Issued
Array ( [id] => 4286892 [patent_doc_number] => 06211082 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-03 [patent_title] => 'Chemical vapor deposition of tungsten using nitrogen-containing gas' [patent_app_type] => 1 [patent_app_number] => 9/021462 [patent_app_country] => US [patent_app_date] => 1998-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 1861 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/211/06211082.pdf [firstpage_image] =>[orig_patent_app_number] => 021462 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/021462
Chemical vapor deposition of tungsten using nitrogen-containing gas Feb 9, 1998 Issued
Array ( [id] => 4178264 [patent_doc_number] => 06037256 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-14 [patent_title] => 'Method for producing a noble metal-containing structure on a substrate, and semiconductor component having such a noble metal-containing structure' [patent_app_type] => 1 [patent_app_number] => 9/015452 [patent_app_country] => US [patent_app_date] => 1998-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 7 [patent_no_of_words] => 2216 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/037/06037256.pdf [firstpage_image] =>[orig_patent_app_number] => 015452 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/015452
Method for producing a noble metal-containing structure on a substrate, and semiconductor component having such a noble metal-containing structure Jan 28, 1998 Issued
Array ( [id] => 4108221 [patent_doc_number] => 06057250 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-02 [patent_title] => 'Low temperature reflow dielectric-fluorinated BPSG' [patent_app_type] => 1 [patent_app_number] => 9/014431 [patent_app_country] => US [patent_app_date] => 1998-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3895 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/057/06057250.pdf [firstpage_image] =>[orig_patent_app_number] => 014431 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/014431
Low temperature reflow dielectric-fluorinated BPSG Jan 26, 1998 Issued
Array ( [id] => 4237600 [patent_doc_number] => 06090705 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-18 [patent_title] => 'Method of eliminating edge effect in chemical vapor deposition of a metal' [patent_app_type] => 1 [patent_app_number] => 9/009387 [patent_app_country] => US [patent_app_date] => 1998-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 3077 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/090/06090705.pdf [firstpage_image] =>[orig_patent_app_number] => 009387 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/009387
Method of eliminating edge effect in chemical vapor deposition of a metal Jan 19, 1998 Issued
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