Brian Green

Array ( [id] => 15565009 [patent_doc_number] => 20200066916 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-27 [patent_title] => Ferroelectric MFM Inductor And Related Circuits [patent_app_type] => utility [patent_app_number] => 16/513429 [patent_app_country] => US [patent_app_date] => 2019-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7406 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16513429 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15045687 [patent_doc_number] => 20190333848 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-31 [patent_title] => GROUND VIA CLUSTERING FOR CROSSTALK MITIGATION [patent_app_type] => utility [patent_app_number] => 16/509387 [patent_app_country] => US [patent_app_date] => 2019-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7610 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16509387 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15367805 [patent_doc_number] => 20200019667 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-16 [patent_title] => SEMICONDUCTOR DEVICE INCLUDING CELL REGION HAVING MOR SIMILAR CELL DENSITIES IN DIFFERENT HEIGHT ROWS, AND METHOD AND SYSTEM FOR GENERATING LAYOUT DIAGRAM OF SAME [patent_app_type] => utility [patent_app_number] => 16/502869 [patent_app_country] => US [patent_app_date] => 2019-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14937 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16502869 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16464079 [patent_doc_number] => 10847439 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-24 [patent_title] => Heat spreaders for use with semiconductor devices [patent_app_type] => utility [patent_app_number] => 16/460941 [patent_app_country] => US [patent_app_date] => 2019-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 4738 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16460941 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16819955 [patent_doc_number] => 11004793 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-11 [patent_title] => Method of forming an interconnect structure having an air gap and structure thereof [patent_app_type] => utility [patent_app_number] => 16/459115 [patent_app_country] => US [patent_app_date] => 2019-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 23 [patent_no_of_words] => 9187 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16459115 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14969123 [patent_doc_number] => 20190312040 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-10 [patent_title] => SRAM Circuits with Aligned Gate Electrodes [patent_app_type] => utility [patent_app_number] => 16/450068 [patent_app_country] => US [patent_app_date] => 2019-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4715 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16450068 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17122102 [patent_doc_number] => 11133244 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-28 [patent_title] => Semiconductor device package and method for manufacturing the same [patent_app_type] => utility [patent_app_number] => 16/446559 [patent_app_country] => US [patent_app_date] => 2019-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 7057 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16446559 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16487806 [patent_doc_number] => 20200381415 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-03 [patent_title] => ELECTROSTATIC DISCHARGE (ESD) PROTECTION DEVICE AND FORMING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/446599 [patent_app_country] => US [patent_app_date] => 2019-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4292 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16446599 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16528797 [patent_doc_number] => 20200402878 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-24 [patent_title] => GROUNDING LIDS IN INTEGRATED CIRCUIT DEVICES [patent_app_type] => utility [patent_app_number] => 16/446388 [patent_app_country] => US [patent_app_date] => 2019-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4839 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16446388 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16410162 [patent_doc_number] => 10818731 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-10-27 [patent_title] => Three-dimensional nonvolatile memory [patent_app_type] => utility [patent_app_number] => 16/446532 [patent_app_country] => US [patent_app_date] => 2019-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 6010 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16446532 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16528757 [patent_doc_number] => 20200402838 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-24 [patent_title] => DIFFUSION BREAK STRUCTURES IN SEMICONDUCTOR DEVICES AND METHODS OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 16/446588 [patent_app_country] => US [patent_app_date] => 2019-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5124 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16446588 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16528830 [patent_doc_number] => 20200402911 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-24 [patent_title] => SEMICONDUCTOR DEVICE PACKAGE [patent_app_type] => utility [patent_app_number] => 16/446368 [patent_app_country] => US [patent_app_date] => 2019-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6108 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16446368 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14875289 [patent_doc_number] => 20190287886 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-19 [patent_title] => PACKAGE INCLUDING MULTIPLE SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 16/429366 [patent_app_country] => US [patent_app_date] => 2019-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10599 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16429366 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14900427 [patent_doc_number] => 20190293979 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-26 [patent_title] => ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/424461 [patent_app_country] => US [patent_app_date] => 2019-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3880 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16424461 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16699945 [patent_doc_number] => 10950553 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-16 [patent_title] => System on integrated chips and methods of forming the same [patent_app_type] => utility [patent_app_number] => 16/422710 [patent_app_country] => US [patent_app_date] => 2019-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 6322 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16422710 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14843081 [patent_doc_number] => 20190279941 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-12 [patent_title] => SEMICONDUCTOR DEVICE PACKAGE [patent_app_type] => utility [patent_app_number] => 16/421238 [patent_app_country] => US [patent_app_date] => 2019-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6163 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16421238 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16773910 [patent_doc_number] => 10985031 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-20 [patent_title] => Semiconductor device and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 16/418563 [patent_app_country] => US [patent_app_date] => 2019-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 35 [patent_no_of_words] => 6100 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16418563 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14752969 [patent_doc_number] => 20190259658 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-22 [patent_title] => Semiconductor Interconnect Structure Having a Graphene Barrier Layer [patent_app_type] => utility [patent_app_number] => 16/399273 [patent_app_country] => US [patent_app_date] => 2019-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11439 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16399273 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16264734 [patent_doc_number] => 10756182 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-25 [patent_title] => Semiconductor device and method of manufacturing semiconductor device [patent_app_type] => utility [patent_app_number] => 16/358705 [patent_app_country] => US [patent_app_date] => 2019-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 10134 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16358705 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14875281 [patent_doc_number] => 20190287882 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-19 [patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/351522 [patent_app_country] => US [patent_app_date] => 2019-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3504 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16351522 [rel_patent_id] =>[rel_patent_doc_number] =>)