Search

Brian Handville

Examiner (ID: 5222, Phone: (571)272-5074 , Office: P/1783 )

Most Active Art Unit
1783
Art Unit(s)
1783
Total Applications
643
Issued Applications
287
Pending Applications
114
Abandoned Applications
267

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19176253 [patent_doc_number] => 20240162227 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-16 [patent_title] => SEMICONDUCTOR DEVICE STRUCTURE INCLUDING FORKSHEET TRANSISTORS AND METHODS OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/513619 [patent_app_country] => US [patent_app_date] => 2023-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12400 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18513619 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/513619
Semiconductor device structure including forksheet transistors and methods of forming the same Nov 18, 2023 Issued
Array ( [id] => 19654423 [patent_doc_number] => 12176223 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-24 [patent_title] => Integrated circuit package supports [patent_app_type] => utility [patent_app_number] => 18/502244 [patent_app_country] => US [patent_app_date] => 2023-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 48 [patent_no_of_words] => 17431 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18502244 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/502244
Integrated circuit package supports Nov 5, 2023 Issued
Array ( [id] => 19936885 [patent_doc_number] => 12310106 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-20 [patent_title] => Devices including stacked nanosheet transistors [patent_app_type] => utility [patent_app_number] => 18/499258 [patent_app_country] => US [patent_app_date] => 2023-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 1011 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18499258 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/499258
Devices including stacked nanosheet transistors Oct 31, 2023 Issued
Array ( [id] => 19671065 [patent_doc_number] => 12183838 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-12-31 [patent_title] => Passivation of infrared detectors using oxide layer [patent_app_type] => utility [patent_app_number] => 18/490456 [patent_app_country] => US [patent_app_date] => 2023-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 2446 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18490456 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/490456
Passivation of infrared detectors using oxide layer Oct 18, 2023 Issued
Array ( [id] => 18943439 [patent_doc_number] => 20240038578 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-01 [patent_title] => CONTINUOUS GATE AND FIN SPACER FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION [patent_app_type] => utility [patent_app_number] => 18/376763 [patent_app_country] => US [patent_app_date] => 2023-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 73531 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 319 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18376763 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/376763
CONTINUOUS GATE AND FIN SPACER FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION Oct 3, 2023 Pending
Array ( [id] => 19392831 [patent_doc_number] => 20240282701 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-22 [patent_title] => Bottom Layer Metal Interconnection Line Structure [patent_app_type] => utility [patent_app_number] => 18/238646 [patent_app_country] => US [patent_app_date] => 2023-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1707 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18238646 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/238646
Bottom Layer Metal Interconnection Line Structure Aug 27, 2023 Pending
Array ( [id] => 19790129 [patent_doc_number] => 20250063808 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-20 [patent_title] => SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/451137 [patent_app_country] => US [patent_app_date] => 2023-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7276 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18451137 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/451137
SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME Aug 16, 2023 Pending
Array ( [id] => 19393026 [patent_doc_number] => 20240282896 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-22 [patent_title] => LIGHT-EMITTING UNIT [patent_app_type] => utility [patent_app_number] => 18/450689 [patent_app_country] => US [patent_app_date] => 2023-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5864 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18450689 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/450689
LIGHT-EMITTING UNIT Aug 15, 2023 Pending
Array ( [id] => 19775632 [patent_doc_number] => 20250057058 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-13 [patent_title] => RESISTIVE MEMORY ELEMENTS WITH A MULTIPLE-MATERIAL ELECTRODE [patent_app_type] => utility [patent_app_number] => 18/232868 [patent_app_country] => US [patent_app_date] => 2023-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3249 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18232868 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/232868
RESISTIVE MEMORY ELEMENTS WITH A MULTIPLE-MATERIAL ELECTRODE Aug 10, 2023 Pending
Array ( [id] => 18812958 [patent_doc_number] => 20230387295 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-30 [patent_title] => VTFET WITH BURIED POWER RAILS [patent_app_type] => utility [patent_app_number] => 18/232510 [patent_app_country] => US [patent_app_date] => 2023-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7804 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18232510 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/232510
VTFET WITH BURIED POWER RAILS Aug 9, 2023 Pending
Array ( [id] => 19775467 [patent_doc_number] => 20250056893 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-13 [patent_title] => SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/366287 [patent_app_country] => US [patent_app_date] => 2023-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21024 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18366287 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/366287
SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME Aug 6, 2023 Pending
Array ( [id] => 19010063 [patent_doc_number] => 20240074134 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-29 [patent_title] => METHOD FOR MANUFACTURING AN INTEGRATED CIRCUIT AND CORRESPONDING INTEGRATED CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/230952 [patent_app_country] => US [patent_app_date] => 2023-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5157 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18230952 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/230952
METHOD FOR MANUFACTURING AN INTEGRATED CIRCUIT AND CORRESPONDING INTEGRATED CIRCUIT Aug 6, 2023 Pending
Array ( [id] => 19670804 [patent_doc_number] => 12183573 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-31 [patent_title] => Device and method for high pressure anneal [patent_app_type] => utility [patent_app_number] => 18/365517 [patent_app_country] => US [patent_app_date] => 2023-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 45 [patent_no_of_words] => 18020 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18365517 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/365517
Device and method for high pressure anneal Aug 3, 2023 Issued
Array ( [id] => 20082606 [patent_doc_number] => 12356707 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-08 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 18/362030 [patent_app_country] => US [patent_app_date] => 2023-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 2383 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18362030 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/362030
Semiconductor device Jul 30, 2023 Issued
Array ( [id] => 18789316 [patent_doc_number] => 20230377969 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-23 [patent_title] => Method of Fabricating Redistribution Circuit Structure [patent_app_type] => utility [patent_app_number] => 18/362083 [patent_app_country] => US [patent_app_date] => 2023-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10969 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18362083 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/362083
Method of fabricating redistribution circuit structure Jul 30, 2023 Issued
Array ( [id] => 19146370 [patent_doc_number] => 20240145400 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-02 [patent_title] => SEMICONDUCTOR DEVICES AND DATA STORAGE SYSTEMS INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/227357 [patent_app_country] => US [patent_app_date] => 2023-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12990 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18227357 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/227357
SEMICONDUCTOR DEVICES AND DATA STORAGE SYSTEMS INCLUDING THE SAME Jul 27, 2023 Pending
Array ( [id] => 19437888 [patent_doc_number] => 20240306386 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-12 [patent_title] => THREE-DIMENSIONAL MEMORY DEVICE CONTAINING COMPOSITE WORD LINES INCLUDING A RESPECTIVE FLUORINE-FREE CAPPING SUBLAYER AND METHODS OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/360474 [patent_app_country] => US [patent_app_date] => 2023-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12287 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18360474 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/360474
THREE-DIMENSIONAL MEMORY DEVICE CONTAINING COMPOSITE WORD LINES INCLUDING A RESPECTIVE FLUORINE-FREE CAPPING SUBLAYER AND METHODS OF FORMING THE SAME Jul 26, 2023 Pending
Array ( [id] => 18789392 [patent_doc_number] => 20230378051 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-23 [patent_title] => CAPACITOR DEVICE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/359122 [patent_app_country] => US [patent_app_date] => 2023-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10238 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18359122 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/359122
CAPACITOR DEVICE AND MANUFACTURING METHOD THEREOF Jul 25, 2023 Pending
Array ( [id] => 18906242 [patent_doc_number] => 20240021727 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-18 [patent_title] => Gate Structure and Method with Enhanced Gate Contact and Threshold Voltage [patent_app_type] => utility [patent_app_number] => 18/355997 [patent_app_country] => US [patent_app_date] => 2023-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9684 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18355997 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/355997
Gate structure and method with enhanced gate contact and threshold voltage Jul 19, 2023 Issued
Array ( [id] => 18943694 [patent_doc_number] => 20240038833 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-01 [patent_title] => CARBON MOLD FOR DRAM CAPACITOR [patent_app_type] => utility [patent_app_number] => 18/222086 [patent_app_country] => US [patent_app_date] => 2023-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6965 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18222086 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/222086
CARBON MOLD FOR DRAM CAPACITOR Jul 13, 2023 Pending
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