
Brian K. Talbot
Examiner (ID: 4069, Phone: (571)272-1428 , Office: P/1715 )
| Most Active Art Unit | 1715 |
| Art Unit(s) | 1715, 1112, 1792, 1762, 1712 |
| Total Applications | 2282 |
| Issued Applications | 1359 |
| Pending Applications | 222 |
| Abandoned Applications | 736 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 20360727
[patent_doc_number] => 12476736
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-11-18
[patent_title] => Concatenated code encoding method, concatenated code decoding method, and communication apparatus
[patent_app_type] => utility
[patent_app_number] => 18/755334
[patent_app_country] => US
[patent_app_date] => 2024-06-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 28
[patent_no_of_words] => 12829
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 227
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18755334
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/755334 | Concatenated code encoding method, concatenated code decoding method, and communication apparatus | Jun 25, 2024 | Issued |
Array
(
[id] => 20181192
[patent_doc_number] => 20250265150
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-08-21
[patent_title] => DECODING OPERATIONS ASSOCIATED WITH ESTIMATED ERROR RATES
[patent_app_type] => utility
[patent_app_number] => 18/751185
[patent_app_country] => US
[patent_app_date] => 2024-06-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4861
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 119
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18751185
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/751185 | DECODING OPERATIONS ASSOCIATED WITH ESTIMATED ERROR RATES | Jun 20, 2024 | Pending |
Array
(
[id] => 19499128
[patent_doc_number] => 20240338146
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-10-10
[patent_title] => Separation of Parity Columns in Bit-Flip Decoding of Low-Density Parity-Check Codes with Pipelining and Column Parallelism
[patent_app_type] => utility
[patent_app_number] => 18/743629
[patent_app_country] => US
[patent_app_date] => 2024-06-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8773
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 139
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18743629
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/743629 | Separation of Parity Columns in Bit-Flip Decoding of Low-Density Parity-Check Codes with Pipelining and Column Parallelism | Jun 13, 2024 | Pending |
Array
(
[id] => 19485266
[patent_doc_number] => 20240333308
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-10-03
[patent_title] => MEMORY, MEMORY MODULE, MEMORY SYSTEM, AND OPERATION METHOD OF MEMORY SYSTEM
[patent_app_type] => utility
[patent_app_number] => 18/738065
[patent_app_country] => US
[patent_app_date] => 2024-06-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7781
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -12
[patent_words_short_claim] => 80
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18738065
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/738065 | MEMORY, MEMORY MODULE, MEMORY SYSTEM, AND OPERATION METHOD OF MEMORY SYSTEM | Jun 9, 2024 | Pending |
Array
(
[id] => 19635392
[patent_doc_number] => 20240413841
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-12-12
[patent_title] => APPARATUSES AND METHODS FOR ECC PARITY BIT REDUCTION
[patent_app_type] => utility
[patent_app_number] => 18/738499
[patent_app_country] => US
[patent_app_date] => 2024-06-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8051
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 73
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18738499
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/738499 | APPARATUSES AND METHODS FOR ECC PARITY BIT REDUCTION | Jun 9, 2024 | Pending |
Array
(
[id] => 19617486
[patent_doc_number] => 20240403166
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-12-05
[patent_title] => METHOD, APPARATUS AND A NON-TRANSITORY MACHINE-READABLE STORAGE MEDIUM INCLUDING FIRMWARE FOR A CXL MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/735239
[patent_app_country] => US
[patent_app_date] => 2024-06-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11031
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 44
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18735239
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/735239 | METHOD, APPARATUS AND A NON-TRANSITORY MACHINE-READABLE STORAGE MEDIUM INCLUDING FIRMWARE FOR A CXL MEMORY DEVICE | Jun 5, 2024 | Pending |
Array
(
[id] => 19485272
[patent_doc_number] => 20240333314
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-10-03
[patent_title] => DECODING DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/734882
[patent_app_country] => US
[patent_app_date] => 2024-06-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10929
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => 0
[patent_words_short_claim] => 291
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18734882
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/734882 | Error correction decoding device | Jun 4, 2024 | Issued |
Array
(
[id] => 19620235
[patent_doc_number] => 20240405915
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-12-05
[patent_title] => POLAR DECODER AND ASSOCIATED METHOD
[patent_app_type] => utility
[patent_app_number] => 18/734486
[patent_app_country] => US
[patent_app_date] => 2024-06-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7423
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 218
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18734486
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/734486 | Polar decoder and associated method | Jun 4, 2024 | Issued |
Array
(
[id] => 19485380
[patent_doc_number] => 20240333422
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-10-03
[patent_title] => Communication Method, Apparatus, and System
[patent_app_type] => utility
[patent_app_number] => 18/673590
[patent_app_country] => US
[patent_app_date] => 2024-05-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 23629
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 120
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18673590
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/673590 | Communication Method, Apparatus, and System | May 23, 2024 | Pending |
Array
(
[id] => 20440356
[patent_doc_number] => 12511192
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-12-30
[patent_title] => Information broadcast techniques for stacked memory architectures
[patent_app_type] => utility
[patent_app_number] => 18/667799
[patent_app_country] => US
[patent_app_date] => 2024-05-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 12483
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 143
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18667799
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/667799 | Information broadcast techniques for stacked memory architectures | May 16, 2024 | Issued |
Array
(
[id] => 20440356
[patent_doc_number] => 12511192
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-12-30
[patent_title] => Information broadcast techniques for stacked memory architectures
[patent_app_type] => utility
[patent_app_number] => 18/667799
[patent_app_country] => US
[patent_app_date] => 2024-05-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 12483
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 143
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18667799
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/667799 | Information broadcast techniques for stacked memory architectures | May 16, 2024 | Issued |
Array
(
[id] => 20403838
[patent_doc_number] => 12493814
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-12-09
[patent_title] => Permanent defect qubit repair system and method using built-in-self-repair model at quantum circuit level
[patent_app_type] => utility
[patent_app_number] => 18/664870
[patent_app_country] => US
[patent_app_date] => 2024-05-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 0
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18664870
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/664870 | Permanent defect qubit repair system and method using built-in-self-repair model at quantum circuit level | May 14, 2024 | Issued |
Array
(
[id] => 19886691
[patent_doc_number] => 12272416
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-04-08
[patent_title] => ATPG testing method for latch based memories, for area reduction
[patent_app_type] => utility
[patent_app_number] => 18/661914
[patent_app_country] => US
[patent_app_date] => 2024-05-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 13
[patent_no_of_words] => 9085
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 197
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18661914
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/661914 | ATPG testing method for latch based memories, for area reduction | May 12, 2024 | Issued |
Array
(
[id] => 19382820
[patent_doc_number] => 20240272690
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-08-15
[patent_title] => TRANSMISSION OF PULSE POWER AND DATA OVER A WIRE PAIR
[patent_app_type] => utility
[patent_app_number] => 18/643013
[patent_app_country] => US
[patent_app_date] => 2024-04-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7623
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18643013
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/643013 | Transmission of pulse power and data over a wire pair | Apr 22, 2024 | Issued |
Array
(
[id] => 19532663
[patent_doc_number] => 20240356565
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-10-24
[patent_title] => ERROR CORRECTION CODE (ECC) CIRCUIT INCLUDING LOW-DENSITY PARITY-CHECK DECODER IN ADAPTIVE OPERATION MODE, OPERATING METHOD OF THE ECC CIRCUIT, AND MEMORY CONTROLLER INCLUDING THE ECC CIRCUIT
[patent_app_type] => utility
[patent_app_number] => 18/643302
[patent_app_country] => US
[patent_app_date] => 2024-04-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8302
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 124
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18643302
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/643302 | ERROR CORRECTION CODE (ECC) CIRCUIT INCLUDING LOW-DENSITY PARITY-CHECK DECODER IN ADAPTIVE OPERATION MODE, OPERATING METHOD OF THE ECC CIRCUIT, AND MEMORY CONTROLLER INCLUDING THE ECC CIRCUIT | Apr 22, 2024 | Issued |
Array
(
[id] => 19560774
[patent_doc_number] => 20240372566
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-11-07
[patent_title] => SELECTIVE MODE ERROR CONTROL
[patent_app_type] => utility
[patent_app_number] => 18/639692
[patent_app_country] => US
[patent_app_date] => 2024-04-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12328
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18639692
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/639692 | SELECTIVE MODE ERROR CONTROL | Apr 17, 2024 | Pending |
Array
(
[id] => 19347416
[patent_doc_number] => 20240256379
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-08-01
[patent_title] => SYSTEMS AND METHODS FOR BLOCKCHAIN REPAIR ASSURANCE TOKENS
[patent_app_type] => utility
[patent_app_number] => 18/629317
[patent_app_country] => US
[patent_app_date] => 2024-04-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8114
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 74
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18629317
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/629317 | Systems and methods for blockchain repair assurance tokens | Apr 7, 2024 | Issued |
Array
(
[id] => 19943440
[patent_doc_number] => 12315576
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-05-27
[patent_title] => Background reads for solid state storage
[patent_app_type] => utility
[patent_app_number] => 18/623342
[patent_app_country] => US
[patent_app_date] => 2024-04-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 23
[patent_no_of_words] => 32458
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 64
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18623342
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/623342 | Background reads for solid state storage | Mar 31, 2024 | Issued |
Array
(
[id] => 20036973
[patent_doc_number] => 20250175195
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-05-29
[patent_title] => CODING CIRCUIT AND MEMORY DEVICE INCLUDING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/620595
[patent_app_country] => US
[patent_app_date] => 2024-03-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 1924
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 85
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18620595
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/620595 | Coding circuit and memory device including the same | Mar 27, 2024 | Issued |
Array
(
[id] => 19303425
[patent_doc_number] => 20240232005
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-07-11
[patent_title] => Efficient Networking for a Distributed Storage System
[patent_app_type] => utility
[patent_app_number] => 18/614833
[patent_app_country] => US
[patent_app_date] => 2024-03-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8246
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18614833
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/614833 | Efficient networking for a distributed storage system | Mar 24, 2024 | Issued |