Search

Brian K. Talbot

Examiner (ID: 4069, Phone: (571)272-1428 , Office: P/1715 )

Most Active Art Unit
1715
Art Unit(s)
1715, 1112, 1792, 1762, 1712
Total Applications
2282
Issued Applications
1359
Pending Applications
222
Abandoned Applications
736

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19686876 [patent_doc_number] => 20250005421 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-02 [patent_title] => UNIVERSAL FAULT-TOLERANT QUANTUM COMPUTATION WITH A 2D ABELIAN TOPOLOGICAL STABILIZER CODE USING MAGIC PATCHES [patent_app_type] => utility [patent_app_number] => 18/344587 [patent_app_country] => US [patent_app_date] => 2023-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18694 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18344587 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/344587
Universal fault-tolerant quantum computation with a 2D abelian topological stabilizer code using magic patches Jun 28, 2023 Issued
Array ( [id] => 18881387 [patent_doc_number] => 20240004756 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-04 [patent_title] => DATA CORRECTION SCHEME WITH REDUCED DEVICE OVERHEAD [patent_app_type] => utility [patent_app_number] => 18/211881 [patent_app_country] => US [patent_app_date] => 2023-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16985 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18211881 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/211881
Data correction scheme with reduced device overhead Jun 19, 2023 Issued
Array ( [id] => 19842545 [patent_doc_number] => 12254944 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-18 [patent_title] => Test system and test method for dynamic random access memory module of intel system [patent_app_type] => utility [patent_app_number] => 18/211496 [patent_app_country] => US [patent_app_date] => 2023-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2684 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18211496 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/211496
Test system and test method for dynamic random access memory module of intel system Jun 18, 2023 Issued
Array ( [id] => 19618008 [patent_doc_number] => 20240403688 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-05 [patent_title] => SINGLE-SHOT ERROR MITIGATION FOR CLIFFORD CIRCUITS [patent_app_type] => utility [patent_app_number] => 18/327693 [patent_app_country] => US [patent_app_date] => 2023-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22871 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18327693 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/327693
Single-shot error mitigation for Clifford circuits May 31, 2023 Issued
Array ( [id] => 19739333 [patent_doc_number] => 12216161 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-04 [patent_title] => Scan chain analysis using predefined capture signature [patent_app_type] => utility [patent_app_number] => 18/323946 [patent_app_country] => US [patent_app_date] => 2023-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 12500 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18323946 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/323946
Scan chain analysis using predefined capture signature May 24, 2023 Issued
Array ( [id] => 19741835 [patent_doc_number] => 12218688 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-04 [patent_title] => Error correction with fast syndrome calculation [patent_app_type] => utility [patent_app_number] => 18/195469 [patent_app_country] => US [patent_app_date] => 2023-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 9190 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18195469 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/195469
Error correction with fast syndrome calculation May 9, 2023 Issued
Array ( [id] => 19843260 [patent_doc_number] => 12255668 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-18 [patent_title] => Error correction with fast syndrome calculation [patent_app_type] => utility [patent_app_number] => 18/195539 [patent_app_country] => US [patent_app_date] => 2023-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 9297 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18195539 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/195539
Error correction with fast syndrome calculation May 9, 2023 Issued
Array ( [id] => 19933510 [patent_doc_number] => 12306714 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-20 [patent_title] => Data memory emulation in flash memory [patent_app_type] => utility [patent_app_number] => 18/313686 [patent_app_country] => US [patent_app_date] => 2023-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 1250 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18313686 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/313686
Data memory emulation in flash memory May 7, 2023 Issued
Array ( [id] => 20118733 [patent_doc_number] => 12368455 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-22 [patent_title] => Flexible and configurable bit error rate reduction for non-volatile memory [patent_app_type] => utility [patent_app_number] => 18/142936 [patent_app_country] => US [patent_app_date] => 2023-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7721 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18142936 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/142936
Flexible and configurable bit error rate reduction for non-volatile memory May 2, 2023 Issued
Array ( [id] => 19061643 [patent_doc_number] => 11940876 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-26 [patent_title] => Selecting storage units based on storage pool traits [patent_app_type] => utility [patent_app_number] => 18/141452 [patent_app_country] => US [patent_app_date] => 2023-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 46 [patent_figures_cnt] => 50 [patent_no_of_words] => 32987 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18141452 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/141452
Selecting storage units based on storage pool traits Apr 29, 2023 Issued
Array ( [id] => 19333705 [patent_doc_number] => 20240248135 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-25 [patent_title] => FORWARD ERROR CORRECTION (FEC) ENCODED PHYSICAL LAYER TEST PATTERN [patent_app_type] => utility [patent_app_number] => 18/304568 [patent_app_country] => US [patent_app_date] => 2023-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7312 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18304568 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/304568
Forward error correction (FEC) encoded physical layer test pattern Apr 20, 2023 Issued
Array ( [id] => 19085258 [patent_doc_number] => 20240112059 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-04 [patent_title] => RAPID MULTI-LEVEL QUBIT RESET [patent_app_type] => utility [patent_app_number] => 18/305152 [patent_app_country] => US [patent_app_date] => 2023-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10365 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18305152 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/305152
Rapid multi-level qubit reset Apr 20, 2023 Issued
Array ( [id] => 18775420 [patent_doc_number] => 20230370255 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-16 [patent_title] => METHOD AND SYSTEM FOR CONTINUOUS-VARIABLE QUANTUM KEY DISTRIBUTION [patent_app_type] => utility [patent_app_number] => 18/131693 [patent_app_country] => US [patent_app_date] => 2023-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6313 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18131693 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/131693
Method and system for continuous-variable quantum key distribution Apr 5, 2023 Issued
Array ( [id] => 18513325 [patent_doc_number] => 20230229555 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-20 [patent_title] => DRAM ASSIST ERROR CORRECTION MECHANISM FOR DDR SDRAM INTERFACE [patent_app_type] => utility [patent_app_number] => 18/127329 [patent_app_country] => US [patent_app_date] => 2023-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8722 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18127329 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/127329
DRAM assist error correction mechanism for DDR SDRAM interface Mar 27, 2023 Issued
Array ( [id] => 20216587 [patent_doc_number] => 12413246 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-09 [patent_title] => Adaptive scaling of parity check messages for LDPC decoding [patent_app_type] => utility [patent_app_number] => 18/864849 [patent_app_country] => US [patent_app_date] => 2023-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 18 [patent_no_of_words] => 6415 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 429 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18864849 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/864849
Adaptive scaling of parity check messages for LDPC decoding Mar 22, 2023 Issued
Array ( [id] => 19655114 [patent_doc_number] => 12176924 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-24 [patent_title] => Deep neural network implementation for concatenated codes [patent_app_type] => utility [patent_app_number] => 18/184916 [patent_app_country] => US [patent_app_date] => 2023-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 21 [patent_no_of_words] => 35966 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18184916 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/184916
Deep neural network implementation for concatenated codes Mar 15, 2023 Issued
Array ( [id] => 19357474 [patent_doc_number] => 12057940 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-06 [patent_title] => Data transmission method and apparatus [patent_app_type] => utility [patent_app_number] => 18/183719 [patent_app_country] => US [patent_app_date] => 2023-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 16427 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18183719 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/183719
Data transmission method and apparatus Mar 13, 2023 Issued
Array ( [id] => 19582364 [patent_doc_number] => 12148490 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-11-19 [patent_title] => At-speed synchronous write-through operation for testing two-port memory [patent_app_type] => utility [patent_app_number] => 18/119738 [patent_app_country] => US [patent_app_date] => 2023-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5273 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18119738 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/119738
At-speed synchronous write-through operation for testing two-port memory Mar 8, 2023 Issued
Array ( [id] => 19328610 [patent_doc_number] => 12046299 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-23 [patent_title] => De-noising using multiple threshold-expert machine learning models [patent_app_type] => utility [patent_app_number] => 18/176597 [patent_app_country] => US [patent_app_date] => 2023-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 14298 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18176597 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/176597
De-noising using multiple threshold-expert machine learning models Feb 28, 2023 Issued
Array ( [id] => 19369426 [patent_doc_number] => 12061506 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-13 [patent_title] => Transmission of pulse power and data over a wire pair [patent_app_type] => utility [patent_app_number] => 18/175668 [patent_app_country] => US [patent_app_date] => 2023-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 7623 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18175668 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/175668
Transmission of pulse power and data over a wire pair Feb 27, 2023 Issued
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