Search

Brian K. Young

Examiner (ID: 16374)

Most Active Art Unit
2819
Art Unit(s)
2819, 2845, 2107, 2104
Total Applications
2839
Issued Applications
2669
Pending Applications
75
Abandoned Applications
102

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11386580 [patent_doc_number] => 20170012636 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-01-12 [patent_title] => 'HYBRID CHARGE-SHARING CHARGE-REDISTRIBUTION DAC FOR SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTERS' [patent_app_type] => utility [patent_app_number] => 15/204365 [patent_app_country] => US [patent_app_date] => 2016-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 13460 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15204365 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/204365
Hybrid charge-sharing charge-redistribution DAC for successive approximation analog-to-digital converters Jul 6, 2016 Issued
Array ( [id] => 13600037 [patent_doc_number] => 20180351567 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-06 [patent_title] => VOLTAGE AMPLIFIER FOR A PROGRAMMABLE VOLTAGE RANGE [patent_app_type] => utility [patent_app_number] => 15/742983 [patent_app_country] => US [patent_app_date] => 2016-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5450 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15742983 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/742983
Voltage amplifier for a programmable voltage range Jul 4, 2016 Issued
Array ( [id] => 12128211 [patent_doc_number] => 20180011796 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-11 [patent_title] => 'Apparatus for Hardware Implementation of Heterogeneous Decompression Processing' [patent_app_type] => utility [patent_app_number] => 15/201697 [patent_app_country] => US [patent_app_date] => 2016-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 24825 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15201697 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/201697
Apparatus for hardware implementation of heterogeneous decompression processing Jul 4, 2016 Issued
Array ( [id] => 11725937 [patent_doc_number] => 09698807 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-07-04 [patent_title] => 'Time signal conversion using dual time-based digital-to-analog converters' [patent_app_type] => utility [patent_app_number] => 15/199257 [patent_app_country] => US [patent_app_date] => 2016-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 22 [patent_no_of_words] => 8376 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15199257 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/199257
Time signal conversion using dual time-based digital-to-analog converters Jun 29, 2016 Issued
Array ( [id] => 11832420 [patent_doc_number] => 09729170 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-08-08 [patent_title] => 'Encoding scheme for processing pulse-amplitude modulated (PAM) signals' [patent_app_type] => utility [patent_app_number] => 15/193635 [patent_app_country] => US [patent_app_date] => 2016-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 9898 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15193635 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/193635
Encoding scheme for processing pulse-amplitude modulated (PAM) signals Jun 26, 2016 Issued
Array ( [id] => 16219182 [patent_doc_number] => 10735008 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-04 [patent_title] => Comparator offset voltage self-correction circuit [patent_app_type] => utility [patent_app_number] => 16/476106 [patent_app_country] => US [patent_app_date] => 2016-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 10969 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 387 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16476106 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/476106
Comparator offset voltage self-correction circuit Jun 26, 2016 Issued
Array ( [id] => 13683813 [patent_doc_number] => 20160380643 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-29 [patent_title] => Reducing Distortion In An Analog-To-Digital Converter [patent_app_type] => utility [patent_app_number] => 15/188272 [patent_app_country] => US [patent_app_date] => 2016-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6081 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15188272 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/188272
Reducing distortion in an analog-to-digital converter Jun 20, 2016 Issued
Array ( [id] => 11679954 [patent_doc_number] => 09678481 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-06-13 [patent_title] => 'Fractional divider using a calibrated digital-to-time converter' [patent_app_type] => utility [patent_app_number] => 15/185378 [patent_app_country] => US [patent_app_date] => 2016-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4624 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15185378 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/185378
Fractional divider using a calibrated digital-to-time converter Jun 16, 2016 Issued
Array ( [id] => 11430575 [patent_doc_number] => 09568889 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-02-14 [patent_title] => 'Time to digital converter with high resolution' [patent_app_type] => utility [patent_app_number] => 15/183752 [patent_app_country] => US [patent_app_date] => 2016-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5339 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15183752 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/183752
Time to digital converter with high resolution Jun 14, 2016 Issued
Array ( [id] => 11354361 [patent_doc_number] => 20160373101 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-22 [patent_title] => 'RC LATTICE DELAY' [patent_app_type] => utility [patent_app_number] => 15/182430 [patent_app_country] => US [patent_app_date] => 2016-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8357 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15182430 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/182430
RC lattice delay Jun 13, 2016 Issued
Array ( [id] => 11681957 [patent_doc_number] => 09680500 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-06-13 [patent_title] => 'Staged data compression, including block level long range compression, for data streams in a communications system' [patent_app_type] => utility [patent_app_number] => 15/176123 [patent_app_country] => US [patent_app_date] => 2016-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 22022 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 282 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15176123 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/176123
Staged data compression, including block level long range compression, for data streams in a communications system Jun 6, 2016 Issued
Array ( [id] => 11869983 [patent_doc_number] => 20170237268 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-17 [patent_title] => 'ANALOG/DIGITAL CONVERTER WITH CHARGE REBALANCED INTEGRATOR' [patent_app_type] => utility [patent_app_number] => 15/169981 [patent_app_country] => US [patent_app_date] => 2016-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 13432 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15169981 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/169981
Analog/digital converter with charge rebalanced integrator May 31, 2016 Issued
Array ( [id] => 11681955 [patent_doc_number] => 09680499 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-06-13 [patent_title] => 'Data compression device and method' [patent_app_type] => utility [patent_app_number] => 15/160105 [patent_app_country] => US [patent_app_date] => 2016-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 8248 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15160105 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/160105
Data compression device and method May 19, 2016 Issued
Array ( [id] => 11496053 [patent_doc_number] => 20170070238 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-09 [patent_title] => 'METHOD FOR LOSSLESS DATA COMPRESSION / DEPRESSION AND DEVICE THEREOF' [patent_app_type] => utility [patent_app_number] => 15/161100 [patent_app_country] => US [patent_app_date] => 2016-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9130 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15161100 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/161100
Method for lossless data compression/decompression and device thereof May 19, 2016 Issued
Array ( [id] => 12742834 [patent_doc_number] => 20180139445 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-17 [patent_title] => Method and Apparatus for Multi-Table Based Context Adaptive Binary Arithmetic Coding [patent_app_type] => utility [patent_app_number] => 15/572600 [patent_app_country] => US [patent_app_date] => 2016-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15871 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15572600 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/572600
Method and apparatus for multi-table based context adaptive binary arithmetic coding May 18, 2016 Issued
Array ( [id] => 11294471 [patent_doc_number] => 20160344403 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-11-24 [patent_title] => 'Zero-offset voltage feedback for AC power supplies' [patent_app_type] => utility [patent_app_number] => 14/999526 [patent_app_country] => US [patent_app_date] => 2016-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4487 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14999526 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/999526
Zero-offset voltage feedback for AC power supplies May 18, 2016 Issued
Array ( [id] => 11057861 [patent_doc_number] => 20160254823 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-01 [patent_title] => 'ELECTRICAL CIRCUIT' [patent_app_type] => utility [patent_app_number] => 15/151236 [patent_app_country] => US [patent_app_date] => 2016-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4870 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15151236 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/151236
Electrical circuit May 9, 2016 Issued
Array ( [id] => 11687915 [patent_doc_number] => 09685969 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-06-20 [patent_title] => 'Time-interleaved high-speed digital-to-analog converter (DAC) architecture with spur calibration' [patent_app_type] => utility [patent_app_number] => 15/141498 [patent_app_country] => US [patent_app_date] => 2016-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5875 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15141498 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/141498
Time-interleaved high-speed digital-to-analog converter (DAC) architecture with spur calibration Apr 27, 2016 Issued
Array ( [id] => 11412394 [patent_doc_number] => 09559714 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-01-31 [patent_title] => 'Analog-to-digital compression' [patent_app_type] => utility [patent_app_number] => 15/136744 [patent_app_country] => US [patent_app_date] => 2016-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6579 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15136744 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/136744
Analog-to-digital compression Apr 21, 2016 Issued
Array ( [id] => 11623230 [patent_doc_number] => 20170133418 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-11 [patent_title] => 'LATCH CIRCUIT, DOUBLE DATA RATE RING COUNTER BASED ON THE LATCH CIRCUIT, HYBRID COUNTING DEVICE, ANALOG-DIGITAL CONVERTING DEVICE, AND CMOS IMAGE SENSOR' [patent_app_type] => utility [patent_app_number] => 15/130697 [patent_app_country] => US [patent_app_date] => 2016-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8360 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15130697 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/130697
Latch circuit, double data rate ring counter based on the latch circuit, hybrid counting device, analog-digital converting device, and CMOS image sensor Apr 14, 2016 Issued
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