Brian K. Young

Array ( [id] => 9402640 [patent_doc_number] => 08692698 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-04-08 [patent_title] => 'Coding device, device for reprocessing a digital baseband signal or intermediate frequency signal, system and method for external digital coding' [patent_app_type] => utility [patent_app_number] => 13/391617 [patent_app_country] => US [patent_app_date] => 2010-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4759 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13391617 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4601262 [patent_doc_number] => 07978099 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-07-12 [patent_title] => '17B/20B coding system' [patent_app_type] => utility [patent_app_number] => 12/847416 [patent_app_country] => US [patent_app_date] => 2010-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 7439 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/978/07978099.pdf [firstpage_image] =>[orig_patent_app_number] => 12847416 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7718007 [patent_doc_number] => 20120007757 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-01-12 [patent_title] => 'DIGITAL-TO-ANALOG CONVERTER (DAC) CALIBRATION SYSTEM' [patent_app_type] => utility [patent_app_number] => 12/834822 [patent_app_country] => US [patent_app_date] => 2010-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10171 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0007/20120007757.pdf [firstpage_image] =>[orig_patent_app_number] => 12834822 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8271186 [patent_doc_number] => 08212694 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-03 [patent_title] => 'Data output circuit' [patent_app_type] => utility [patent_app_number] => 12/833089 [patent_app_country] => US [patent_app_date] => 2010-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 2563 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12833089 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8386989 [patent_doc_number] => 08264393 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-09-11 [patent_title] => 'Current reduction in a single stage cyclic analog to digital converter with variable resolution' [patent_app_type] => utility [patent_app_number] => 12/833597 [patent_app_country] => US [patent_app_date] => 2010-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 9814 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 32 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12833597 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8029915 [patent_doc_number] => 08144039 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-03-27 [patent_title] => 'Semiconductor integrated device' [patent_app_type] => utility [patent_app_number] => 12/832367 [patent_app_country] => US [patent_app_date] => 2010-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 8169 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/144/08144039.pdf [firstpage_image] =>[orig_patent_app_number] => 12832367 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8364545 [patent_doc_number] => 08253614 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-08-28 [patent_title] => 'Analog-to-digital conversion methods and systems' [patent_app_type] => utility [patent_app_number] => 12/832352 [patent_app_country] => US [patent_app_date] => 2010-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3114 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12832352 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8295261 [patent_doc_number] => 08223053 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-17 [patent_title] => '2-phase gain calibration and scaling scheme for switched capacitor sigma-delta modulator' [patent_app_type] => utility [patent_app_number] => 12/832599 [patent_app_country] => US [patent_app_date] => 2010-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 19 [patent_no_of_words] => 10517 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12832599 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6132018 [patent_doc_number] => 20110006937 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-01-13 [patent_title] => 'Delta-Sigma-Delta Modulator' [patent_app_type] => utility [patent_app_number] => 12/832703 [patent_app_country] => US [patent_app_date] => 2010-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8907 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0006/20110006937.pdf [firstpage_image] =>[orig_patent_app_number] => 12832703 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8181255 [patent_doc_number] => 20120112934 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-10 [patent_title] => 'METHOD FOR VECTOR QUANTIZATION OF A FEATURE VECTOR' [patent_app_type] => utility [patent_app_number] => 13/319806 [patent_app_country] => US [patent_app_date] => 2010-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3669 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0112/20120112934.pdf [firstpage_image] =>[orig_patent_app_number] => 13319806 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6092113 [patent_doc_number] => 20110001765 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-01-06 [patent_title] => 'Semiconductor integrated circuit and liquid crystal drive circuit' [patent_app_type] => utility [patent_app_number] => 12/801592 [patent_app_country] => US [patent_app_date] => 2010-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 12932 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20110001765.pdf [firstpage_image] =>[orig_patent_app_number] => 12801592 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7683153 [patent_doc_number] => 20100241258 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-23 [patent_title] => 'System and Method to Modify a Metadata Parameter' [patent_app_type] => utility [patent_app_number] => 12/790542 [patent_app_country] => US [patent_app_date] => 2010-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7508 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0241/20100241258.pdf [firstpage_image] =>[orig_patent_app_number] => 12790542 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8206401 [patent_doc_number] => 20120127004 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-24 [patent_title] => 'A/D CONVERSION INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 13/322375 [patent_app_country] => US [patent_app_date] => 2010-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 13406 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0127/20120127004.pdf [firstpage_image] =>[orig_patent_app_number] => 13322375 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8245545 [patent_doc_number] => 08203475 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-06-19 [patent_title] => 'Parallel mash ΔΣ modulator' [patent_app_type] => utility [patent_app_number] => 12/785895 [patent_app_country] => US [patent_app_date] => 2010-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2190 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/203/08203475.pdf [firstpage_image] =>[orig_patent_app_number] => 12785895 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6146508 [patent_doc_number] => 20110018751 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-01-27 [patent_title] => 'FOLDING ANALOG-TO-DIGITAL CONVERTER' [patent_app_type] => utility [patent_app_number] => 12/784781 [patent_app_country] => US [patent_app_date] => 2010-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9304 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0018/20110018751.pdf [firstpage_image] =>[orig_patent_app_number] => 12784781 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6380020 [patent_doc_number] => 20100302081 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-02 [patent_title] => 'PARALLEL-SERIAL CONVERTER' [patent_app_type] => utility [patent_app_number] => 12/783951 [patent_app_country] => US [patent_app_date] => 2010-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 16015 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0302/20100302081.pdf [firstpage_image] =>[orig_patent_app_number] => 12783951 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7565493 [patent_doc_number] => 20110285556 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-24 [patent_title] => 'Parallel Compression for Dictionary-Based Sequential Coders' [patent_app_type] => utility [patent_app_number] => 12/782892 [patent_app_country] => US [patent_app_date] => 2010-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4514 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0285/20110285556.pdf [firstpage_image] =>[orig_patent_app_number] => 12782892 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8592858 [patent_doc_number] => 08350735 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-01-08 [patent_title] => 'Method for coding and an apparatus' [patent_app_type] => utility [patent_app_number] => 12/783067 [patent_app_country] => US [patent_app_date] => 2010-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 7079 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12783067 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6564328 [patent_doc_number] => 20100289683 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-11-18 [patent_title] => 'REFERENCE VOLTAGE GENERATION CIRCUIT, A/D CONVERTER AND D/A CONVERTER' [patent_app_type] => utility [patent_app_number] => 12/781304 [patent_app_country] => US [patent_app_date] => 2010-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4465 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0289/20100289683.pdf [firstpage_image] =>[orig_patent_app_number] => 12781304 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8215640 [patent_doc_number] => 08193953 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-06-05 [patent_title] => 'Data width scaler circuitry' [patent_app_type] => utility [patent_app_number] => 12/780478 [patent_app_country] => US [patent_app_date] => 2010-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 8771 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/193/08193953.pdf [firstpage_image] =>[orig_patent_app_number] => 12780478 [rel_patent_id] =>[rel_patent_doc_number] =>)